diff options
| author | Roland McGrath <roland@hack.frob.com> | 2011-08-14 15:46:52 -0700 |
|---|---|---|
| committer | Roland McGrath <roland@hack.frob.com> | 2011-08-14 19:26:49 -0700 |
| commit | 5744c68d78f6ca6c6500e2c8d3d85b3a31f4ed2a (patch) | |
| tree | 598e4e47557fc1df03d6e01e60f89a48c8cc5fa4 /nptl | |
| parent | 85ae058936c5f6e2bf7fb26979389dd26c9690b5 (diff) | |
| download | glibc-5744c68d78f6ca6c6500e2c8d3d85b3a31f4ed2a.tar.gz glibc-5744c68d78f6ca6c6500e2c8d3d85b3a31f4ed2a.tar.xz glibc-5744c68d78f6ca6c6500e2c8d3d85b3a31f4ed2a.zip | |
Align x86 TCB to 64 bytes (cache line size), important for Atom.
Diffstat (limited to 'nptl')
| -rw-r--r-- | nptl/ChangeLog | 5 | ||||
| -rw-r--r-- | nptl/sysdeps/i386/pthreaddef.h | 12 | ||||
| -rw-r--r-- | nptl/sysdeps/x86_64/pthreaddef.h | 16 |
3 files changed, 26 insertions, 7 deletions
diff --git a/nptl/ChangeLog b/nptl/ChangeLog index 1dc5f20815..40d90e73f3 100644 --- a/nptl/ChangeLog +++ b/nptl/ChangeLog @@ -1,3 +1,8 @@ +2011-08-14 Roland McGrath <roland@hack.frob.com> + + * sysdeps/i386/pthreaddef.h (TCB_ALIGNMENT): Set to 64, optimal on Atom. + * sysdeps/x86_64/pthreaddef.h (TCB_ALIGNMENT): Likewise. + 2011-08-08 Andreas Schwab <schwab@redhat.com> * sysdeps/unix/sysv/linux/x86_64/cancellation.S: Maintain aligned diff --git a/nptl/sysdeps/i386/pthreaddef.h b/nptl/sysdeps/i386/pthreaddef.h index 43b771c6db..1e840664bf 100644 --- a/nptl/sysdeps/i386/pthreaddef.h +++ b/nptl/sysdeps/i386/pthreaddef.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2002, 2003 Free Software Foundation, Inc. +/* Copyright (C) 2002,2003,2011 Free Software Foundation, Inc. This file is part of the GNU C Library. Contributed by Ulrich Drepper <drepper@redhat.com>, 2002. @@ -27,8 +27,14 @@ /* Minimal stack size after allocating thread descriptor and guard size. */ #define MINIMAL_REST_STACK 2048 -/* Alignment requirement for TCB. */ -#define TCB_ALIGNMENT 16 +/* Alignment requirement for TCB. + + Some processors such as Intel Atom pay a big penalty on every + access using a segment override if that segment's base is not + aligned to the size of a cache line. (See Intel 64 and IA-32 + Architectures Optimization Reference Manual, section 13.3.3.3, + "Segment Base".) On such machines, a cache line is 64 bytes. */ +#define TCB_ALIGNMENT 64 /* Location of current stack frame. */ diff --git a/nptl/sysdeps/x86_64/pthreaddef.h b/nptl/sysdeps/x86_64/pthreaddef.h index 8ec135c048..9de4af2b69 100644 --- a/nptl/sysdeps/x86_64/pthreaddef.h +++ b/nptl/sysdeps/x86_64/pthreaddef.h @@ -1,4 +1,4 @@ -/* Copyright (C) 2002, 2003, 2007 Free Software Foundation, Inc. +/* Copyright (C) 2002,2003,2007,2011 Free Software Foundation, Inc. This file is part of the GNU C Library. Contributed by Ulrich Drepper <drepper@redhat.com>, 2002. @@ -27,9 +27,17 @@ /* Minimal stack size after allocating thread descriptor and guard size. */ #define MINIMAL_REST_STACK 2048 -/* Alignment requirement for TCB. Need to store post-AVX vector registers - in the TCB and we want the storage to be aligned at 32-byte. */ -#define TCB_ALIGNMENT 32 +/* Alignment requirement for TCB. + + We need to store post-AVX vector registers in the TCB and we want the + storage to be aligned to at least 32 bytes. + + Some processors such as Intel Atom pay a big penalty on every + access using a segment override if that segment's base is not + aligned to the size of a cache line. (See Intel 64 and IA-32 + Architectures Optimization Reference Manual, section 13.3.3.3, + "Segment Base".) On such machines, a cache line is 64 bytes. */ +#define TCB_ALIGNMENT 64 /* Location of current stack frame. The frame pointer is not usable. */ |