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authorRoland McGrath <roland@hack.frob.com>2011-08-14 15:46:52 -0700
committerRoland McGrath <roland@hack.frob.com>2011-08-14 19:26:49 -0700
commit5744c68d78f6ca6c6500e2c8d3d85b3a31f4ed2a (patch)
tree598e4e47557fc1df03d6e01e60f89a48c8cc5fa4 /nptl/sysdeps
parent85ae058936c5f6e2bf7fb26979389dd26c9690b5 (diff)
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Align x86 TCB to 64 bytes (cache line size), important for Atom.
Diffstat (limited to 'nptl/sysdeps')
-rw-r--r--nptl/sysdeps/i386/pthreaddef.h12
-rw-r--r--nptl/sysdeps/x86_64/pthreaddef.h16
2 files changed, 21 insertions, 7 deletions
diff --git a/nptl/sysdeps/i386/pthreaddef.h b/nptl/sysdeps/i386/pthreaddef.h
index 43b771c6db..1e840664bf 100644
--- a/nptl/sysdeps/i386/pthreaddef.h
+++ b/nptl/sysdeps/i386/pthreaddef.h
@@ -1,4 +1,4 @@
-/* Copyright (C) 2002, 2003 Free Software Foundation, Inc.
+/* Copyright (C) 2002,2003,2011 Free Software Foundation, Inc.
    This file is part of the GNU C Library.
    Contributed by Ulrich Drepper <drepper@redhat.com>, 2002.
 
@@ -27,8 +27,14 @@
 /* Minimal stack size after allocating thread descriptor and guard size.  */
 #define MINIMAL_REST_STACK	2048
 
-/* Alignment requirement for TCB.  */
-#define TCB_ALIGNMENT		16
+/* Alignment requirement for TCB.
+
+   Some processors such as Intel Atom pay a big penalty on every
+   access using a segment override if that segment's base is not
+   aligned to the size of a cache line.  (See Intel 64 and IA-32
+   Architectures Optimization Reference Manual, section 13.3.3.3,
+   "Segment Base".)  On such machines, a cache line is 64 bytes.  */
+#define TCB_ALIGNMENT		64
 
 
 /* Location of current stack frame.  */
diff --git a/nptl/sysdeps/x86_64/pthreaddef.h b/nptl/sysdeps/x86_64/pthreaddef.h
index 8ec135c048..9de4af2b69 100644
--- a/nptl/sysdeps/x86_64/pthreaddef.h
+++ b/nptl/sysdeps/x86_64/pthreaddef.h
@@ -1,4 +1,4 @@
-/* Copyright (C) 2002, 2003, 2007 Free Software Foundation, Inc.
+/* Copyright (C) 2002,2003,2007,2011 Free Software Foundation, Inc.
    This file is part of the GNU C Library.
    Contributed by Ulrich Drepper <drepper@redhat.com>, 2002.
 
@@ -27,9 +27,17 @@
 /* Minimal stack size after allocating thread descriptor and guard size.  */
 #define MINIMAL_REST_STACK	2048
 
-/* Alignment requirement for TCB.  Need to store post-AVX vector registers
-   in the TCB and we want the storage to be aligned at 32-byte.  */
-#define TCB_ALIGNMENT		32
+/* Alignment requirement for TCB.
+
+   We need to store post-AVX vector registers in the TCB and we want the
+   storage to be aligned to at least 32 bytes.
+
+   Some processors such as Intel Atom pay a big penalty on every
+   access using a segment override if that segment's base is not
+   aligned to the size of a cache line.  (See Intel 64 and IA-32
+   Architectures Optimization Reference Manual, section 13.3.3.3,
+   "Segment Base".)  On such machines, a cache line is 64 bytes.  */
+#define TCB_ALIGNMENT		64
 
 
 /* Location of current stack frame.  The frame pointer is not usable.  */