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| author | H.J. Lu <hjl.tools@gmail.com> | 2016-05-13 13:26:37 -0700 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2016-05-20 14:57:00 -0700 |
| commit | 0c559041b832f64f754824c8b125b7a3af08b722 (patch) | |
| tree | ba22ad15b12384768a6a6466dda76a8c17de9b72 /misc/efgcvt_r.c | |
| parent | b7598b1b855b39628104feb9a1f6151a86351a64 (diff) | |
| download | glibc-hjl/cache/master.tar.gz glibc-hjl/cache/master.tar.xz glibc-hjl/cache/master.zip | |
Count number of logical processors sharing L2 cache hjl/cache/master
For Intel processors, when there are both L2 and L3 caches, SMT level type should be ued to count number of available logical processors sharing L2 cache. If there is only L2 cache, core level type should be used to count number of available logical processors sharing L2 cache. Number of available logical processors sharing L2 cache should be used for non-inclusive L2 and L3 caches. * sysdeps/x86/cacheinfo.c (init_cacheinfo): Count number of available logical processors with SMT level type sharing L2 cache for Intel processors.
Diffstat (limited to 'misc/efgcvt_r.c')
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