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| author | Wilco Dijkstra <wdijkstr@arm.com> | 2018-11-20 12:37:00 +0000 |
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| committer | Wilco Dijkstra <wdijkstr@arm.com> | 2018-11-20 12:37:00 +0000 |
| commit | 5770c0ad1e0c784e817464ca2cf9436a58c9beb7 (patch) | |
| tree | 6616d15f2d44823b4c70b0fe607b4c7927fe45ac /math/w_sinhl_compat.c | |
| parent | 9a62a9397d0a25643922d8d053f04ee895100d9a (diff) | |
| download | glibc-5770c0ad1e0c784e817464ca2cf9436a58c9beb7.tar.gz glibc-5770c0ad1e0c784e817464ca2cf9436a58c9beb7.tar.xz glibc-5770c0ad1e0c784e817464ca2cf9436a58c9beb7.zip | |
[AArch64] Adjust writeback in non-zero memset
This fixes an ineffiency in the non-zero memset. Delaying the writeback until the end of the loop is slightly faster on some cores - this shows ~5% performance gain on Cortex-A53 when doing large non-zero memsets. * sysdeps/aarch64/memset.S (MEMSET): Improve non-zero memset loop.
Diffstat (limited to 'math/w_sinhl_compat.c')
0 files changed, 0 insertions, 0 deletions