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| author | Wilco Dijkstra <Wilco.Dijkstra@arm.com> | 2018-12-19 18:28:24 +0000 |
|---|---|---|
| committer | Wilco Dijkstra <wdijkstr@arm.com> | 2019-09-06 18:58:34 +0100 |
| commit | d6613ad24f708706c24bffa38351e26e1dd5b5d1 (patch) | |
| tree | 2fe98d347a0827a5eb1806d644a506f227a841bd /manual | |
| parent | ad64510e5c74729108a02a6c22f03aa8ee07a8d3 (diff) | |
| download | glibc-d6613ad24f708706c24bffa38351e26e1dd5b5d1.tar.gz glibc-d6613ad24f708706c24bffa38351e26e1dd5b5d1.tar.xz glibc-d6613ad24f708706c24bffa38351e26e1dd5b5d1.zip | |
[AArch64] Add ifunc support for Ares
Add Ares to the midr_el0 list and support ifunc dispatch. Since Ares supports 2 128-bit loads/stores, use Neon registers for memcpy by selecting __memcpy_falkor by default (we should rename this to __memcpy_simd or similar). * manual/tunables.texi (glibc.cpu.name): Add ares tunable. * sysdeps/aarch64/multiarch/memcpy.c (__libc_memcpy): Use __memcpy_falkor for ares. * sysdeps/unix/sysv/linux/aarch64/cpu-features.h (IS_ARES): Add new define. * sysdeps/unix/sysv/linux/aarch64/cpu-features.c (cpu_list): Add ares cpu. (cherry picked from commit 02f440c1ef5d5d79552a524065aa3e2fabe469b9)
Diffstat (limited to 'manual')
| -rw-r--r-- | manual/tunables.texi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/manual/tunables.texi b/manual/tunables.texi index a23c8d076a..b230cde556 100644 --- a/manual/tunables.texi +++ b/manual/tunables.texi @@ -253,7 +253,7 @@ This tunable is specific to i386 and x86-64. @deftp Tunable glibc.tune.cpu The @code{glibc.tune.cpu=xxx} tunable allows the user to tell @theglibc{} to assume that the CPU is @code{xxx} where xxx may have one of these values: -@code{generic}, @code{falkor}, @code{thunderxt88}. +@code{generic}, @code{falkor}, @code{thunderxt88}, @code{ares}. This tunable is specific to aarch64. @end deftp |