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authorH.J. Lu <hjl.tools@gmail.com>2020-09-15 05:49:27 -0700
committerH.J. Lu <hjl.tools@gmail.com>2020-09-16 05:56:10 -0700
commitf2c679d4b2c73a95f437c705f960a4af1fa23498 (patch)
tree1f30bd0a05a25caa79dda87c9330fb7c6de901bd /manual
parenta140ff9162f353e804d6a8c83c8f3c18511850dd (diff)
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<sys/platform/x86.h>: Add Intel Key Locker support
Add Intel Key Locker:

https://software.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html

support to <sys/platform/x86.h>.  Intel Key Locker has

1. KL: AES Key Locker instructions.
2. WIDE_KL: AES wide Key Locker instructions.
3. AESKLE: AES Key Locker instructions are enabled by OS.

Applications should use

if (CPU_FEATURE_USABLE (KL))

and

if (CPU_FEATURE_USABLE (WIDE_KL))

to check if AES Key Locker instructions and AES wide Key Locker
instructions are usable.
Diffstat (limited to 'manual')
-rw-r--r--manual/platform.texi9
1 files changed, 9 insertions, 0 deletions
diff --git a/manual/platform.texi b/manual/platform.texi
index 2c145acdc3..95b0ed0642 100644
--- a/manual/platform.texi
+++ b/manual/platform.texi
@@ -178,6 +178,9 @@ The supported processor features are:
 @code{AES} -- The AES instruction extensions.
 
 @item
+@code{AESKLE} -- AES Key Locker instructions are enabled by OS.
+
+@item
 @code{AMX_BF16} -- Tile computational operations on bfloat16 numbers.
 
 @item
@@ -354,6 +357,9 @@ the indirect branch predictor barrier (IBPB).
 @code{INVPCID} -- INVPCID instruction.
 
 @item
+@code{KL} -- AES Key Locker instructions.
+
+@item
 @code{L1D_FLUSH} -- IA32_FLUSH_CMD MSR.
 
 @item
@@ -599,6 +605,9 @@ using a TSC deadline value.
 @code{WBNOINVD} -- WBINVD/WBNOINVD instructions.
 
 @item
+@code{WIDE_KL} -- AES wide Key Locker instructions.
+
+@item
 @code{X2APIC} -- x2APIC.
 
 @item