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authorH.J. Lu <hjl.tools@gmail.com>2016-05-27 15:16:22 -0700
committerH.J. Lu <hjl.tools@gmail.com>2016-06-06 13:23:12 -0700
commitb60dda5f2385aaca873069f9fb28645b82a1b711 (patch)
treec54066243106b06dce48a10c0021de0570ec7747 /localedata/locales/de_BE
parented46697862f2b0c2db726cc4c772e6003914bd72 (diff)
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Count number of logical processors sharing L2 cache hjl/erms/2.22
For Intel processors, when there are both L2 and L3 caches, SMT level
type should be ued to count number of available logical processors
sharing L2 cache.  If there is only L2 cache, core level type should
be used to count number of available logical processors sharing L2
cache.  Number of available logical processors sharing L2 cache should
be used for non-inclusive L2 and L3 caches.

	* sysdeps/x86/cacheinfo.c (init_cacheinfo): Count number of
	available logical processors with SMT level type sharing L2
	cache for Intel processors.
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