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| author | Zong Li <zongbox@gmail.com> | 2018-11-30 17:16:38 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-08-27 08:17:42 -0700 |
| commit | 941a55cf590ed23fdca9efff291f1ef82112bd6f (patch) | |
| tree | 7fe7351bda1831df355e731cf490c5899879f898 /iconv/tst-iconv3.c | |
| parent | 5b6113d62efabb123db433b14adddd4a5fb6b7ec (diff) | |
| download | glibc-941a55cf590ed23fdca9efff291f1ef82112bd6f.tar.gz glibc-941a55cf590ed23fdca9efff291f1ef82112bd6f.tar.xz glibc-941a55cf590ed23fdca9efff291f1ef82112bd6f.zip | |
RISC-V: Add hard float support for 32-bit CPUs
This patch adds support for hardware floating-point support for the RV32IF and RV32IFD platforms. Reviewed-by: Maciej W. Rozycki <macro@wdc.com>
Diffstat (limited to 'iconv/tst-iconv3.c')
0 files changed, 0 insertions, 0 deletions