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author | Aurelien Jarno <aurelien@aurel32.net> | 2022-01-17 19:41:40 +0100 |
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committer | Aurelien Jarno <aurelien@aurel32.net> | 2022-01-17 19:49:44 +0100 |
commit | a51b76b71e8190a50b0e0c0b32f313888b930108 (patch) | |
tree | 11f3cb6646f262308a731d7715b08d023262e1be /htl | |
parent | 55b99e9ed07688019609bd4dcd17d3ebf4572948 (diff) | |
download | glibc-a51b76b71e8190a50b0e0c0b32f313888b930108.tar.gz glibc-a51b76b71e8190a50b0e0c0b32f313888b930108.tar.xz glibc-a51b76b71e8190a50b0e0c0b32f313888b930108.zip |
x86: use default cache size if it cannot be determined [BZ #28784]
In some cases (e.g QEMU, non-Intel/AMD CPU) the cache information can not be retrieved and the corresponding values are set to 0. Commit 2d651eb9265d ("x86: Move x86 processor cache info to cpu_features") changed the behaviour in such case by defining the __x86_shared_cache_size and __x86_data_cache_size variables to 0 instead of using the default values. This cause an issue with the i686 SSE2 optimized bzero/routine which assumes that the cache size is at least 128 bytes, and otherwise tries to zero/set the whole address space minus 128 bytes. Fix that by restoring the original code to only update __x86_shared_cache_size and __x86_data_cache_size variables if the corresponding cache sizes are not zero. Fixes bug 28784 Fixes commit 2d651eb9265d Reviewed-by: H.J. Lu <hjl.tools@gmail.com> (cherry picked from commit c242fcce06e3102ca663b2f992611d0bda4f2668)
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