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author | H.J. Lu <hjl.tools@gmail.com> | 2021-06-30 10:47:06 -0700 |
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committer | H.J. Lu <hjl.tools@gmail.com> | 2021-07-01 10:47:35 -0700 |
commit | ea8e465a6b8d0f26c72bcbe453a854de3abf68ec (patch) | |
tree | f0b6b62b393ea4715f75248e5425d088a8aeba14 /hesiod/nss_hesiod/hesiod-service.c | |
parent | b1b4f7209ecaad4bf9a5d0d2ef1338409d364bac (diff) | |
download | glibc-ea8e465a6b8d0f26c72bcbe453a854de3abf68ec.tar.gz glibc-ea8e465a6b8d0f26c72bcbe453a854de3abf68ec.tar.xz glibc-ea8e465a6b8d0f26c72bcbe453a854de3abf68ec.zip |
x86: Check RTM_ALWAYS_ABORT for RTM [BZ #28033]
From https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html * Intel TSX will be disabled by default. * The processor will force abort all Restricted Transactional Memory (RTM) transactions by default. * A new CPUID bit CPUID.07H.0H.EDX[11](RTM_ALWAYS_ABORT) will be enumerated, which is set to indicate to updated software that the loaded microcode is forcing RTM abort. * On processors that enumerate support for RTM, the CPUID enumeration bits for Intel TSX (CPUID.07H.0H.EBX[11] and CPUID.07H.0H.EBX[4]) continue to be set by default after microcode update. * Workloads that were benefited from Intel TSX might experience a change in performance. * System software may use a new bit in Model-Specific Register (MSR) 0x10F TSX_FORCE_ABORT[TSX_CPUID_CLEAR] functionality to clear the Hardware Lock Elision (HLE) and RTM bits to indicate to software that Intel TSX is disabled. 1. Add RTM_ALWAYS_ABORT to CPUID features. 2. Set RTM usable only if RTM_ALWAYS_ABORT isn't set. This skips the string/tst-memchr-rtm etc. testcases on the affected processors, which always fail after a microcde update. 3. Check RTM feature, instead of usability, against /proc/cpuinfo. This fixes BZ #28033.
Diffstat (limited to 'hesiod/nss_hesiod/hesiod-service.c')
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