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author | H.J. Lu <hjl.tools@gmail.com> | 2017-08-14 05:54:25 -0700 |
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committer | H.J. Lu <hjl.tools@gmail.com> | 2017-08-14 05:54:38 -0700 |
commit | 73322d5ff6ad71c65f875095c4801771cff9ab2d (patch) | |
tree | 6dfe6b618b2501adfed46076a4d06cc3b4b0b5e0 /elf/tst-order-a3.c | |
parent | dbc303ef76503793b4744004984d248346602479 (diff) | |
download | glibc-73322d5ff6ad71c65f875095c4801771cff9ab2d.tar.gz glibc-73322d5ff6ad71c65f875095c4801771cff9ab2d.tar.xz glibc-73322d5ff6ad71c65f875095c4801771cff9ab2d.zip |
x86: Add IBT/SHSTK bits to cpu-features
Add IBT/SHSTK bits to cpu-features for Shadow Stack in Intel Control-flow Enforcement Technology (CET) instructions: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf * sysdeps/x86/cpu-features.h (bit_cpu_BIT): New. (bit_cpu_SHSTK): Likewise. (index_cpu_IBT): Likewise. (index_cpu_SHSTK): Likewise. (reg_IBT): Likewise. (reg_SHSTK): Likewise. * sysdeps/x86/cpu-tunables.c (TUNABLE_CALLBACK (set_hwcaps)): Handle index_cpu_IBT and index_cpu_SHSTK.
Diffstat (limited to 'elf/tst-order-a3.c')
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