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| author | Patrick McGehearty <patrick.mcgehearty@oracle.com> | 2017-12-13 18:14:17 -0200 |
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| committer | Adhemerval Zanella <adhemerval.zanella@linaro.org> | 2017-12-14 08:48:19 -0200 |
| commit | e6a1c5dc776dd6b562e0aae17dbb61e396a81fb3 (patch) | |
| tree | aef723c8d6802c2037d83824bf0a905dfe758974 /bits | |
| parent | 1b6e07f8e06240eff4f0d0a53161508de582cbc6 (diff) | |
| download | glibc-e6a1c5dc776dd6b562e0aae17dbb61e396a81fb3.tar.gz glibc-e6a1c5dc776dd6b562e0aae17dbb61e396a81fb3.tar.xz glibc-e6a1c5dc776dd6b562e0aae17dbb61e396a81fb3.zip | |
sparc: M7 optimized memset/bzero
Support added to identify Sparc M7/T7/S7/M8/T8 processor capability. Performance tests run on Sparc S7 using new code and old niagara4 code. Optimizations for memset also apply to bzero as they share code. For memset/bzero, performance comparison with niagara4 code: For memset nonzero data, 256-1023 bytes - 60-90% gain (in cache); 5% gain (out of cache) 1K+ bytes - 80-260% gain (in cache); 40-80% gain (out of cache) For memset zero data (and bzero), 256-1023 bytes - 80-120% gain (in cache), 0% gain (out of cache) 1024+ bytes - 2-4x gain (in cache), 10-35% gain (out of cache) Tested in sparcv9-*-* and sparc64-*-* targets in both multi and non-multi arch configurations. Patrick McGehearty <patrick.mcgehearty@oracle.com> Adhemerval Zanella <adhemerval.zanella@linaro.org> * sysdeps/sparc/sparc32/sparcv9/multiarch/Makefile (sysdeps_routines): Add memset-niagara7. * sysdeps/sparc/sparc64/multiarch/Makefile (sysdes_rotuines): Likewise. * sysdeps/sparc/sparc32/sparcv9/multiarch/memset-niagara7.S: New file. * sysdeps/sparc/sparc64/multiarch/memset-niagara7.S: Likewise. * sysdeps/sparc/sparc64/multiarch/ifunc-impl-list.c (__libc_ifunc_impl_list): Add __bzero_niagara7 and __memset_niagara7. * sysdeps/sparc/sparc64/multiarch/ifunc-memset.h (IFUNC_SELECTOR): Add niagara7 option. * NEWS: Mention sparc m7 optimized memcpy, mempcpy, memmove, and memset.
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