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| author | Adhemerval Zanella <adhemerval.zanella@linaro.org> | 2018-10-11 15:18:40 -0300 |
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| committer | Adhemerval Zanella <adhemerval.zanella@linaro.org> | 2018-10-23 14:57:02 -0300 |
| commit | c3d8dc45c9df199b8334599a6cbd98c9950dba62 (patch) | |
| tree | 723bf34e95345abb6fe13f4afa6f4821a317b92e /assert/tst-assert-c++.cc | |
| parent | f1034472e21d77b978464b73adbb0f9f1f032c91 (diff) | |
| download | glibc-c3d8dc45c9df199b8334599a6cbd98c9950dba62.tar.gz glibc-c3d8dc45c9df199b8334599a6cbd98c9950dba62.tar.xz glibc-c3d8dc45c9df199b8334599a6cbd98c9950dba62.zip | |
x86: Fix Haswell strong flags (BZ#23709)
Th commit 'Disable TSX on some Haswell processors.' (2702856bf4) changed the default flags for Haswell models. Previously, new models were handled by the default switch path, which assumed a Core i3/i5/i7 if AVX is available. After the patch, Haswell models (0x3f, 0x3c, 0x45, 0x46) do not set the flags Fast_Rep_String, Fast_Unaligned_Load, Fast_Unaligned_Copy, and Prefer_PMINUB_for_stringop (only the TSX one). This patch fixes it by disentangle the TSX flag handling from the memory optimization ones. The strstr case cited on patch now selects the __strstr_sse2_unaligned as expected for the Haswell cpu. Checked on x86_64-linux-gnu. [BZ #23709] * sysdeps/x86/cpu-features.c (init_cpu_features): Set TSX bits independently of other flags.
Diffstat (limited to 'assert/tst-assert-c++.cc')
0 files changed, 0 insertions, 0 deletions