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| author | H.J. Lu <hjl.tools@gmail.com> | 2018-05-21 10:54:20 -0700 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2018-05-21 10:54:32 -0700 |
| commit | 1af30adcd59fae929371d3a56b239861b1088a6e (patch) | |
| tree | c8f904764ad403e83910455fd229a092db003b74 /ChangeLog | |
| parent | 7c67e6e8b9815d18f548f9c54444adaef17c0a6e (diff) | |
| download | glibc-1af30adcd59fae929371d3a56b239861b1088a6e.tar.gz glibc-1af30adcd59fae929371d3a56b239861b1088a6e.tar.xz glibc-1af30adcd59fae929371d3a56b239861b1088a6e.zip | |
Initial Fast Short REP MOVSB (FSRM) support
The newer Intel processors support Fast Short REP MOVSB which has a feature bit in CPUID. This patch adds the Fast Short REP MOVSB (FSRM) bit to x86 cpu-features. * sysdeps/x86/cpu-features.h (bit_cpu_FSRM): New. (index_cpu_FSRM): Likewise. (reg_FSRM): Likewise.
Diffstat (limited to 'ChangeLog')
| -rw-r--r-- | ChangeLog | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/ChangeLog b/ChangeLog index 6e9b14cffe..c8ff9d45c8 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,9 @@ +2018-05-21 H.J. Lu <hongjiu.lu@intel.com> + + * sysdeps/x86/cpu-features.h (bit_cpu_FSRM): New. + (index_cpu_FSRM): Likewise. + (reg_FSRM): Likewise. + 2018-05-18 Joseph Myers <joseph@codesourcery.com> * math/gen-tgmath-tests.py: Import sys. |