diff options
| author | Paul A. Clarke <pc@us.ibm.com> | 2019-09-19 14:04:45 -0500 |
|---|---|---|
| committer | Paul A. Clarke <pc@us.ibm.com> | 2019-09-27 11:03:25 -0500 |
| commit | d7a568af5546e0313abbc04060c8e9b0d3f750b4 (patch) | |
| tree | 80878e5e076ca9ae78089ee80b321c1d057e3f80 /ChangeLog | |
| parent | 36c17c7079a5243a890ba43affff326a041775a9 (diff) | |
| download | glibc-d7a568af5546e0313abbc04060c8e9b0d3f750b4.tar.gz glibc-d7a568af5546e0313abbc04060c8e9b0d3f750b4.tar.xz glibc-d7a568af5546e0313abbc04060c8e9b0d3f750b4.zip | |
[powerpc] Rename fesetenv_mode to fesetenv_control
fesetenv_mode is used variously to write the FPSCR exception enable bits and rounding mode bits. These are referred to as the control bits in the POWER ISA. Change the name to be reflective of its current and expected use, and match up well with fegetenv_control.
Diffstat (limited to 'ChangeLog')
| -rw-r--r-- | ChangeLog | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/ChangeLog b/ChangeLog index 3c792b4317..d9ea94ad70 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,5 +1,16 @@ 2019-09-27 Paul A. Clarke <pc@us.ibm.com> + * sysdeps/powerpc/fpu/fenv_libc.h (fesetenv_mode): Rename to + fesetenv_control. + * sysdeps/powerpc/fpu/fedisblxcpt.c (fedisableexcept): Accommodate + rename of fesetenv_mode to fegetenv_control. + * sysdeps/powerpc/fpu/feenablxcpt.c (feenableexcept): Likewise. + * sysdeps/powerpc/fpu/fesetmode.c (fesetmode): Likewise. + * sysdeps/powerpc/fpu/fenv_private.h (__libc_femergeenv_ppc): Likewise. + (libc_feholdsetround_noex_ppc_ctx): Likewise. + +2019-09-27 Paul A. Clarke <pc@us.ibm.com> + * sysdeps/powerpc/fpu/fenv_private.h (libc_feholdsetround_noex_ppc_ctx): Call fesetenv_mode instead of fesetenv_register. |