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| author | Adhemerval Zanella <azanella@linux.vnet.ibm.com> | 2014-04-28 14:38:24 -0500 |
|---|---|---|
| committer | Adhemerval Zanella <azanella@linux.vnet.ibm.com> | 2014-04-29 07:05:39 -0500 |
| commit | 18f2945ae9216cfcd53a162080a73e3d719de9e6 (patch) | |
| tree | 8d529fe01c41f0d3c6dd290aa69dbf4e5d6e083f /ChangeLog | |
| parent | 5abebba403181de898bbea4ee1bcce5f088c663b (diff) | |
| download | glibc-18f2945ae9216cfcd53a162080a73e3d719de9e6.tar.gz glibc-18f2945ae9216cfcd53a162080a73e3d719de9e6.tar.xz glibc-18f2945ae9216cfcd53a162080a73e3d719de9e6.zip | |
PowerPC: Suppress unnecessary FPSCR write
This patch optimizes the FPSCR update on exception and rounding change functions by just updating its value if new value if different from current one. It also optimizes fedisableexcept and feenableexcept by removing an unecessary FPSCR read.
Diffstat (limited to 'ChangeLog')
| -rw-r--r-- | ChangeLog | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/ChangeLog b/ChangeLog index 8b9cfb5bdb..4007295165 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,15 @@ +2014-04-28 Adhemerval Zanella <azanella@linux.vnet.ibm.com> + + * sysdeps/powerpc/fpu/fclrexcpt.c (__feclearexcept): Do not update + FPSCR if value do not change. + * sysdeps/powerpc/fpu/fedisblxcpt.c (fedisableexcept): Likewise. + * sysdeps/powerpc/fpu/feenablxcpt.c (feenableexcept): Likewise. + * sysdeps/powerpc/fpu/feholdexcpt.c (feholdexcept): Likewise. + * sysdeps/powerpc/fpu/fesetenv.c (__fesetenv): Likewise. + * sysdeps/powerpc/fpu/fsetexcptflg.c (__fesetexceptflag): Likewise. + * sysdeps/powerpc/fpu/fenv_libc.h (fenv_reg_to_exceptions): New helper + function. + 2014-05-29 Carlos O'Donell <carlos@systemhalted.org> * sysdeps/hppa: Move directory from ports/sysdeps/hppa. |