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| author | Liubov Dmitrieva <liubov.dmitrieva@intel.com> | 2013-06-28 15:28:50 -0700 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2013-06-28 15:31:40 -0700 |
| commit | 6308fd9a46a2f4aa550886e6f58190fb209ef027 (patch) | |
| tree | 668039e1091165b38354a1ffebf35b0058de3eed /ChangeLog | |
| parent | 89cd956937f46e8f4a0374994965f991642dd408 (diff) | |
| download | glibc-6308fd9a46a2f4aa550886e6f58190fb209ef027.tar.gz glibc-6308fd9a46a2f4aa550886e6f58190fb209ef027.tar.xz glibc-6308fd9a46a2f4aa550886e6f58190fb209ef027.zip | |
Skip SSE4.2 versions on Intel Silvermont
SSE2/SSSE3 versions are faster than SSE4.2 versions on Intel Silvermont.
Diffstat (limited to 'ChangeLog')
| -rw-r--r-- | ChangeLog | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/ChangeLog b/ChangeLog index c5551b805e..406ca28bd2 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,17 @@ +2013-06-28 Liubov Dmitrieva <liubov.dmitrieva@intel.com> + + * sysdeps/x86_64/multiarch/init-arch.c (__init_cpu_features): Set + bit_Slow_SSE4_2 and bit_Prefer_PMINUB_for_stringop for Intel + Silvermont. + * sysdeps/x86_64/multiarch/init-arch.h (bit_Slow_SSE4_2): New + macro. + (index_Slow_SSE4_2): Likewise. + (index_Prefer_PMINUB_for_stringop): Likewise. + * sysdeps/x86_64/multiarch/strchr.S: Skip SSE4.2 version if + bit_Slow_SSE4_2 is set. + * sysdeps/x86_64/multiarch/strcmp.S: Likewise. + * sysdeps/x86_64/multiarch/strrchr.S: Likewise. + 2013-06-28 Ryan S. Arnold <rsa@linux.vnet.ibm.com> * sysdeps/powerpc/Makefile: Add comment about generating an offset to |