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author | Wilco <wdijkstr@arm.com> | 2014-06-24 12:04:27 +0000 |
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committer | Wilco <wdijkstr@arm.com> | 2014-06-24 12:04:27 +0000 |
commit | 001f7b773c637560ecfa686452a5e68d60d07db3 (patch) | |
tree | 08bd670c6b892304a287c56f6cbeb00e92276567 /ChangeLog | |
parent | 4841e6a6c2fa691201fb52dfaf6b6a8920229bac (diff) | |
download | glibc-001f7b773c637560ecfa686452a5e68d60d07db3.tar.gz glibc-001f7b773c637560ecfa686452a5e68d60d07db3.tar.xz glibc-001f7b773c637560ecfa686452a5e68d60d07db3.zip |
Speed up the ARM fenv implementation by avoiding unnecessary FPSCR
writes if the FPSCR remains unchanged. 2014-06-24 Wilco <wdijkstr@arm.com> * sysdeps/arm/fclrexcpt.c (feclearexcept): Optimize to avoid unnecessary FPSCR writes. * sysdeps/arm/fedisblxcpt.c (fedisableexcept): Likewise. * sysdeps/arm/feenablxcpt.c (feenableexcept): Likewise. * sysdeps/arm/fsetexcptflg.c (fesetexceptflag): Likewise. * sysdeps/arm/setfpucw.c (__setfpucw): Likewise.
Diffstat (limited to 'ChangeLog')
-rw-r--r-- | ChangeLog | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/ChangeLog b/ChangeLog index 28bc633e37..0b0f61affa 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,5 +1,14 @@ 2014-06-24 Wilco <wdijkstr@arm.com> + * sysdeps/arm/fclrexcpt.c (feclearexcept): + Optimize to avoid unnecessary FPSCR writes. + * sysdeps/arm/fedisblxcpt.c (fedisableexcept): Likewise. + * sysdeps/arm/feenablxcpt.c (feenableexcept): Likewise. + * sysdeps/arm/fsetexcptflg.c (fesetexceptflag): Likewise. + * sysdeps/arm/setfpucw.c (__setfpucw): Likewise. + +2014-06-24 Wilco <wdijkstr@arm.com> + * sysdeps/arm/fegetround.c (fegetround): Call get_rounding_mode. * sysdeps/arm/feholdexcpt.c (feholdexcept): Call libc_feholdexcept_vfp. * sysdeps/arm/fesetround.c (fesetround): Call libc_fesetround_vfp. |