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| author | H.J. Lu <hjl.tools@gmail.com> | 2021-06-30 10:47:06 -0700 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2022-02-01 08:27:13 -0800 |
| commit | 277331ee2131f9972e4f7a7bbc78ed32920647e7 (patch) | |
| tree | c7075a617f2ce687a9317c99d5733f5cafd95b44 | |
| parent | b0fcf886725f666e3406069fe33166bedc1efa91 (diff) | |
| download | glibc-277331ee2131f9972e4f7a7bbc78ed32920647e7.tar.gz glibc-277331ee2131f9972e4f7a7bbc78ed32920647e7.tar.xz glibc-277331ee2131f9972e4f7a7bbc78ed32920647e7.zip | |
x86: Check RTM_ALWAYS_ABORT for RTM [BZ #28033]
From https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html * Intel TSX will be disabled by default. * The processor will force abort all Restricted Transactional Memory (RTM) transactions by default. * A new CPUID bit CPUID.07H.0H.EDX[11](RTM_ALWAYS_ABORT) will be enumerated, which is set to indicate to updated software that the loaded microcode is forcing RTM abort. * On processors that enumerate support for RTM, the CPUID enumeration bits for Intel TSX (CPUID.07H.0H.EBX[11] and CPUID.07H.0H.EBX[4]) continue to be set by default after microcode update. * Workloads that were benefited from Intel TSX might experience a change in performance. * System software may use a new bit in Model-Specific Register (MSR) 0x10F TSX_FORCE_ABORT[TSX_CPUID_CLEAR] functionality to clear the Hardware Lock Elision (HLE) and RTM bits to indicate to software that Intel TSX is disabled. 1. Add RTM_ALWAYS_ABORT to CPUID features. 2. Set RTM usable only if RTM_ALWAYS_ABORT isn't set. This skips the string/tst-memchr-rtm etc. testcases on the affected processors, which always fail after a microcde update. 3. Check RTM feature, instead of usability, against /proc/cpuinfo. This fixes BZ #28033. (cherry picked from commit ea8e465a6b8d0f26c72bcbe453a854de3abf68ec)
| -rw-r--r-- | sysdeps/x86/cpu-features.c | 3 | ||||
| -rw-r--r-- | sysdeps/x86/cpu-features.h | 3 |
2 files changed, 6 insertions, 0 deletions
diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c index 4be4be7051..90be104842 100644 --- a/sysdeps/x86/cpu-features.c +++ b/sysdeps/x86/cpu-features.c @@ -248,6 +248,9 @@ init_cpu_features (struct cpu_features *cpu_features) get_extended_indices (cpu_features); + if (CPU_FEATURES_CPU_P (cpu_features, RTM_ALWAYS_ABORT)) + cpu_features->cpuid[index_cpu_RTM].reg_RTM &= ~bit_cpu_RTM; + if (family == 0x06) { model += extended_model; diff --git a/sysdeps/x86/cpu-features.h b/sysdeps/x86/cpu-features.h index 177aa0ebc8..aad6c5198d 100644 --- a/sysdeps/x86/cpu-features.h +++ b/sysdeps/x86/cpu-features.h @@ -81,6 +81,7 @@ #define bit_cpu_IBT (1u << 20) #define bit_cpu_SHSTK (1u << 7) #define bit_cpu_FSRM (1 << 4) +#define bit_cpu_RTM_ALWAYS_ABORT (1 << 11) /* XCR0 Feature flags. */ #define bit_XMM_state (1 << 1) @@ -213,6 +214,7 @@ extern const struct cpu_features *__get_cpu_features (void) # define index_cpu_IBT COMMON_CPUID_INDEX_7 # define index_cpu_SHSTK COMMON_CPUID_INDEX_7 # define index_cpu_FSRM COMMON_CPUID_INDEX_7 +# define index_cpu_RTM_ALWAYS_ABORT COMMON_CPUID_INDEX_7 # define reg_CX8 edx # define reg_CMOV edx @@ -245,6 +247,7 @@ extern const struct cpu_features *__get_cpu_features (void) # define reg_IBT edx # define reg_SHSTK ecx # define reg_FSRM edx +# define reg_RTM_ALWAYS_ABORT edx # define index_arch_Fast_Rep_String FEATURE_INDEX_1 # define index_arch_Fast_Copy_Backward FEATURE_INDEX_1 |