diff options
| author | David S. Miller <davem@davemloft.net> | 2012-03-15 00:11:17 -0700 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2012-03-15 00:14:55 -0700 |
| commit | 559398ab746fd7dbbe09e847813a1b917b9ded14 (patch) | |
| tree | eb94365dc148695185aa9788d812c7211679cf2f | |
| parent | 5a1c1e32435486a52561d2801dece286b1c32984 (diff) | |
| download | glibc-559398ab746fd7dbbe09e847813a1b917b9ded14.tar.gz glibc-559398ab746fd7dbbe09e847813a1b917b9ded14.tar.xz glibc-559398ab746fd7dbbe09e847813a1b917b9ded14.zip | |
Add more sparc VIS3 optimized math routines.
* sysdeps/sparc/sparc64/fpu/multiarch/s_ceil-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_ceil.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_finite-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_finite.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_finitef-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_finitef.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_floor-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_floor.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_floorf-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_floorf.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_isinf-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_isinf.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_isinff-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_isinff.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_isnan-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_isnan.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_isnanf-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_isnanf.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_lrint-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_lrint.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_lrintf-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_lrintf.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_rint-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_rint.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_rintf-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_rintf.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/Makefile: Add new VIS3 routines. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil-vis3.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf-vis3.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs-vis3.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf-vis3.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor-vis3.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf-vis3.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrint-vis3.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrint.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrintf-vis3.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrintf.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rint-vis3.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rint.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rintf-vis3.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rintf.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrt-vis3.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrt.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrtf-vis3.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrtf.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/Makefile: Add new VIS3 routines. * sysdeps/sparc/sparc32/sparcv9/fpu/unix/sysv/linux/multiarch/Implies: New file.
56 files changed, 2656 insertions, 11 deletions
diff --git a/ChangeLog b/ChangeLog index f79bcbf353..48823daae1 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,5 +1,63 @@ 2012-03-14 David S. Miller <davem@davemloft.net> + * sysdeps/sparc/sparc64/fpu/multiarch/s_ceil-vis3.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_ceil.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf-vis3.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_finite-vis3.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_finite.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_finitef-vis3.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_finitef.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_floor-vis3.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_floor.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_floorf-vis3.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_floorf.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_isinf-vis3.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_isinf.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_isinff-vis3.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_isinff.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_isnan-vis3.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_isnan.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_isnanf-vis3.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_isnanf.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_lrint-vis3.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_lrint.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_lrintf-vis3.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_lrintf.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_rint-vis3.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_rint.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_rintf-vis3.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/s_rintf.S: New file. + * sysdeps/sparc/sparc64/fpu/multiarch/Makefile: Add new VIS3 routines. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil-vis3.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf-vis3.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs-vis3.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf-vis3.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor-vis3.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf-vis3.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrint-vis3.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrint.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrintf-vis3.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrintf.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rint-vis3.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rint.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rintf-vis3.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rintf.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrt-vis3.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrt.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrtf-vis3.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrtf.S: New file. + * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/Makefile: Add new VIS3 routines. + + * sysdeps/sparc/sparc32/sparcv9/fpu/unix/sysv/linux/multiarch/Implies: + New file. + * sysdeps/sparc/fpu/libm-test-ulps: Update. * sysdeps/sparc/configure.in: New file. diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/Makefile b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/Makefile index 33b03ac6aa..3a7a389380 100644 --- a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/Makefile +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/Makefile @@ -1,9 +1,9 @@ ifeq ($(subdir),math) ifeq ($(have-as-vis3),yes) -libm-sysdep_routines += m_copysignf-vis3 m_copysign-vis3 +libm-sysdep_routines += m_copysignf-vis3 m_copysign-vis3 s_ceilf-vis3 \ + s_ceil-vis3 s_fabs-vis3 s_fabsf-vis3 s_floor-vis3 \ + s_floorf-vis3 s_llrintf-vis3 s_llrint-vis3 \ + s_rintf-vis3 s_rint-vis3 w_sqrt-vis3 w_sqrtf-vis3 sysdep_routines += s_copysignf-vis3 s_copysign-vis3 - -CFLAGS-s_copysignf-vis3.S = -Wa,-Av9d -CFLAGS-s_copysign-vis3.S = -Wa,-Av9d endif -endif \ No newline at end of file +endif diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil-vis3.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil-vis3.S new file mode 100644 index 0000000000..be41219cef --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil-vis3.S @@ -0,0 +1,78 @@ +/* ceil function, sparc32 v9 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* Since changing the rounding mode is extremely expensive, we + try to round up using a method that is rounding mode + agnostic. + + We add then subtract (or subtract than add if the initial + value was negative) 2**23 to the value, then subtract it + back out. + + This will clear out the fractional portion of the value. + One of two things will happen for non-whole initial values. + Either the rounding mode will round it up, or it will be + rounded down. If the value started out whole, it will be + equal after the addition and subtraction. This means we + can accurately detect with one test whether we need to add + another 1.0 to round it up properly. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ +#define ONE_DOT_ZERO 0x3ff00000 /* 1.0 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__ceil_vis3) + sethi %hi(TWO_FIFTYTWO), %o2 + sllx %o0, 32, %o0 + sethi %hi(ONE_DOT_ZERO), %o3 + or %o0, %o1, %o0 + movxtod %o0, %f0 + sllx %o2, 32, %o2 + fzero ZERO + sllx %o3, 32, %o3 + + fnegd ZERO, SIGN_BIT + + movxtod %o2, %f16 + fabsd %f0, %f14 + + fcmpd %fcc3, %f14, %f16 + + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + + for %f16, SIGN_BIT, %f16 + faddd %f0, %f16, %f18 + fsubd %f18, %f16, %f18 + fcmpd %fcc2, %f18, %f0 + movxtod %o3, %f20 + + fmovduge %fcc2, ZERO, %f20 + faddd %f18, %f20, %f0 + fabsd %f0, %f0 + retl + for %f0, SIGN_BIT, %f0 +END (__ceil_vis3) diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil.S new file mode 100644 index 0000000000..f91fda61b9 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil.S @@ -0,0 +1,46 @@ +#include <sysdep.h> + + .text +ENTRY(__ceil) + .type __ceil, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__ceil_vis3), %o1 + xor %o1, %gdop_lox10(__ceil_vis3), %o1 +# else + set __ceil_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__ceil_generic), %o1 + xor %o1, %gdop_lox10(__ceil_generic), %o1 +# else + set __ceil_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__ceil) +weak_alias (__ceil, ceil) + +# undef weak_alias +# define weak_alias(a, b) + +#define __ceil __ceil_generic + +#include "../s_ceil.S" diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf-vis3.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf-vis3.S new file mode 100644 index 0000000000..c35a85f24f --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf-vis3.S @@ -0,0 +1,74 @@ +/* Float ceil function, sparc32 v9 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* Since changing the rounding mode is extremely expensive, we + try to round up using a method that is rounding mode + agnostic. + + We add then subtract (or subtract than add if the initial + value was negative) 2**23 to the value, then subtract it + back out. + + This will clear out the fractional portion of the value. + One of two things will happen for non-whole initial values. + Either the rounding mode will round it up, or it will be + rounded down. If the value started out whole, it will be + equal after the addition and subtraction. This means we + can accurately detect with one test whether we need to add + another 1.0 to round it up properly. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ +#define ONE_DOT_ZERO 0x3f800000 /* 1.0 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__ceilf_vis3) + movwtos %o0, %f0 + sethi %hi(TWO_TWENTYTHREE), %o2 + sethi %hi(ONE_DOT_ZERO), %o3 + fzeros ZERO + + fnegs ZERO, SIGN_BIT + + movwtos %o2, %f16 + fabss %f0, %f14 + + fcmps %fcc3, %f14, %f16 + + fmovsuge %fcc3, ZERO, %f16 + fands %f0, SIGN_BIT, SIGN_BIT + + fors %f16, SIGN_BIT, %f16 + fadds %f0, %f16, %f1 + fsubs %f1, %f16, %f1 + fcmps %fcc2, %f1, %f0 + movwtos %o3, %f9 + + fmovsuge %fcc2, ZERO, %f9 + fadds %f1, %f9, %f0 + fabss %f0, %f0 + retl + fors %f0, SIGN_BIT, %f0 +END (__ceilf_vis3) diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf.S new file mode 100644 index 0000000000..048b6195d8 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf.S @@ -0,0 +1,46 @@ +#include <sysdep.h> + + .text +ENTRY(__ceilf) + .type __ceilf, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__ceilf_vis3), %o1 + xor %o1, %gdop_lox10(__ceilf_vis3), %o1 +# else + set __ceilf_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__ceilf_generic), %o1 + xor %o1, %gdop_lox10(__ceilf_generic), %o1 +# else + set __ceilf_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__ceilf) +weak_alias (__ceilf, ceilf) + +# undef weak_alias +# define weak_alias(a, b) + +#define __ceilf __ceilf_generic + +#include "../s_ceilf.S" diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs-vis3.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs-vis3.S new file mode 100644 index 0000000000..733ec90e42 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs-vis3.S @@ -0,0 +1,26 @@ +/* Float absolute value, sparc32+v9 vis3 version. + Copyright (C) 2011 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__fabs_vis3) + movwtos %o0, %f0 + movwtos %o1, %f1 + retl + fabsd %f0, %f0 +END (__fabs_vis3) diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs.S new file mode 100644 index 0000000000..ed70e4be2c --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs.S @@ -0,0 +1,46 @@ +#include <sysdep.h> + + .text +ENTRY(__fabs) + .type __fabs, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__fabs_vis3), %o1 + xor %o1, %gdop_lox10(__fabs_vis3), %o1 +# else + set __fabs_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__fabs_generic), %o1 + xor %o1, %gdop_lox10(__fabs_generic), %o1 +# else + set __fabs_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__fabs) +weak_alias (__fabs, fabs) + +# undef weak_alias +# define weak_alias(a, b) + +#define __fabs __fabs_generic + +#include "../s_fabs.S" diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf-vis3.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf-vis3.S new file mode 100644 index 0000000000..82b577580e --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf-vis3.S @@ -0,0 +1,26 @@ +/* Float absolute value, sparc32 vis3 version. + Copyright (C) 2006 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jakub Jelinek <jakub@redhat.com>, 2006. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__fabsf_vis3) + movwtos %o0, %f0 + retl + fabss %f0, %f0 +END (__fabsf_vis3) diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf.S new file mode 100644 index 0000000000..4b7351fc2e --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf.S @@ -0,0 +1,46 @@ +#include <sysdep.h> + + .text +ENTRY(__fabsf) + .type __fabsf, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__fabsf_vis3), %o1 + xor %o1, %gdop_lox10(__fabsf_vis3), %o1 +# else + set __fabsf_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__fabsf_generic), %o1 + xor %o1, %gdop_lox10(__fabsf_generic), %o1 +# else + set __fabsf_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__fabsf) +weak_alias (__fabsf, fabsf) + +# undef weak_alias +# define weak_alias(a, b) + +#define __fabsf __fabsf_generic + +#include "../../../fpu/s_fabsf.S" diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor-vis3.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor-vis3.S new file mode 100644 index 0000000000..d7e5d24c17 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor-vis3.S @@ -0,0 +1,79 @@ +/* floor function, sparc32 v9 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* Since changing the rounding mode is extremely expensive, we + try to round up using a method that is rounding mode + agnostic. + + We add then subtract (or subtract than add if the initial + value was negative) 2**23 to the value, then subtract it + back out. + + This will clear out the fractional portion of the value. + One of two things will happen for non-whole initial values. + Either the rounding mode will round it up, or it will be + rounded down. If the value started out whole, it will be + equal after the addition and subtraction. This means we + can accurately detect with one test whether we need to add + another 1.0 to round it up properly. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ +#define ONE_DOT_ZERO 0x3ff00000 /* 1.0 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__floor_vis3) + sethi %hi(TWO_FIFTYTWO), %o2 + sllx %o0, 32, %o0 + sethi %hi(ONE_DOT_ZERO), %o3 + or %o0, %o1, %o0 + movxtod %o0, %f0 + sllx %o2, 32, %o2 + fzero ZERO + sllx %o3, 32, %o3 + + fnegd ZERO, SIGN_BIT + + stx %o2, [%sp + 72] + fabsd %f0, %f14 + + ldd [%sp + 72], %f16 + fcmpd %fcc3, %f14, %f16 + + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + + for %f16, SIGN_BIT, %f16 + faddd %f0, %f16, %f18 + fsubd %f18, %f16, %f18 + fcmpd %fcc2, %f18, %f0 + movxtod %o3, %f20 + + fmovdule %fcc2, ZERO, %f20 + fsubd %f18, %f20, %f0 + fabsd %f0, %f0 + retl + for %f0, SIGN_BIT, %f0 +END (__floor_vis3) diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor.S new file mode 100644 index 0000000000..1cdc53fb84 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor.S @@ -0,0 +1,46 @@ +#include <sysdep.h> + + .text +ENTRY(__floor) + .type __floor, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__floor_vis3), %o1 + xor %o1, %gdop_lox10(__floor_vis3), %o1 +# else + set __floor_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__floor_generic), %o1 + xor %o1, %gdop_lox10(__floor_generic), %o1 +# else + set __floor_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__floor) +weak_alias (__floor, floor) + +# undef weak_alias +# define weak_alias(a, b) + +#define __floor __floor_generic + +#include "../s_floor.S" diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf-vis3.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf-vis3.S new file mode 100644 index 0000000000..24c8764fa6 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf-vis3.S @@ -0,0 +1,74 @@ +/* Float floor function, sparc32 v9 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* Since changing the rounding mode is extremely expensive, we + try to round up using a method that is rounding mode + agnostic. + + We add then subtract (or subtract than add if the initial + value was negative) 2**23 to the value, then subtract it + back out. + + This will clear out the fractional portion of the value. + One of two things will happen for non-whole initial values. + Either the rounding mode will round it up, or it will be + rounded down. If the value started out whole, it will be + equal after the addition and subtraction. This means we + can accurately detect with one test whether we need to add + another 1.0 to round it up properly. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ +#define ONE_DOT_ZERO 0x3f800000 /* 1.0 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__floorf_vis3) + movwtos %o0, %f0 + sethi %hi(TWO_TWENTYTHREE), %o2 + sethi %hi(ONE_DOT_ZERO), %o3 + fzeros ZERO + + fnegs ZERO, SIGN_BIT + + movwtos %o2, %f16 + fabss %f0, %f14 + + fcmps %fcc3, %f14, %f16 + + fmovsuge %fcc3, ZERO, %f16 + fands %f0, SIGN_BIT, SIGN_BIT + + fors %f16, SIGN_BIT, %f16 + fadds %f0, %f16, %f1 + fsubs %f1, %f16, %f1 + fcmps %fcc2, %f1, %f0 + movwtos %o3, %f9 + + fmovsule %fcc2, ZERO, %f9 + fsubs %f1, %f9, %f0 + fabss %f0, %f0 + retl + fors %f0, SIGN_BIT, %f0 +END (__floorf_vis3) diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf.S new file mode 100644 index 0000000000..0dcd0e1431 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf.S @@ -0,0 +1,46 @@ +#include <sysdep.h> + + .text +ENTRY(__floorf) + .type __floorf, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__floorf_vis3), %o1 + xor %o1, %gdop_lox10(__floorf_vis3), %o1 +# else + set __floorf_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__floorf_generic), %o1 + xor %o1, %gdop_lox10(__floorf_generic), %o1 +# else + set __floorf_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__floorf) +weak_alias (__floorf, floorf) + +# undef weak_alias +# define weak_alias(a, b) + +#define __floorf __floorf_generic + +#include "../s_floorf.S" diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrint-vis3.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrint-vis3.S new file mode 100644 index 0000000000..8a90722b54 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrint-vis3.S @@ -0,0 +1,58 @@ +/* llrint(), sparc32 v9 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__llrint_vis3) + sethi %hi(TWO_FIFTYTWO), %o2 + sllx %o0, 32, %o0 + + or %o0, %o1, %o0 + fzero ZERO + + movxtod %o0, %f0 + sllx %o2, 32, %o2 + fnegd ZERO, SIGN_BIT + + movxtod %o2, %f16 + fabsd %f0, %f14 + + fcmpd %fcc3, %f14, %f16 + + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + + for %f16, SIGN_BIT, %f16 + faddd %f0, %f16, %f6 + fsubd %f6, %f16, %f0 + fabsd %f0, %f0 + for %f0, SIGN_BIT, %f0 + fdtox %f0, %f4 + movstouw %f4, %o0 + retl + movstouw %f5, %o1 +END (__llrint_vis3) diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrint.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrint.S new file mode 100644 index 0000000000..3a9294d3a8 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrint.S @@ -0,0 +1,51 @@ +#include <sysdep.h> + + .text +ENTRY(__llrint) + .type __llrint, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__llrint_vis3), %o1 + xor %o1, %gdop_lox10(__llrint_vis3), %o1 +# else + set __llrint_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__llrint_generic), %o1 + xor %o1, %gdop_lox10(__llrint_generic), %o1 +# else + set __llrint_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__llrint) +weak_alias (__llrint, llrint) + +strong_alias (__llrint, __lllrint) +weak_alias (__lllrint, lllrint) + +# undef weak_alias +# define weak_alias(a, b) +# undef strong_alias +# define strong_alias(a, b) + +#define __llrint __llrint_generic + +#include "../s_llrint.S" diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrintf-vis3.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrintf-vis3.S new file mode 100644 index 0000000000..8590af2bb4 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrintf-vis3.S @@ -0,0 +1,54 @@ +/* llrintf(), sparc32 v9 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__llrintf_vis3) + movwtos %o0, %f1 + sethi %hi(TWO_TWENTYTHREE), %o2 + fzeros ZERO + + fnegs ZERO, SIGN_BIT + + movwtos %o2, %f16 + fabss %f1, %f14 + + fcmps %fcc3, %f14, %f16 + + fmovsuge %fcc3, ZERO, %f16 + fands %f1, SIGN_BIT, SIGN_BIT + + fors %f16, SIGN_BIT, %f16 + fadds %f1, %f16, %f5 + fsubs %f5, %f16, %f0 + fabss %f0, %f0 + fors %f0, SIGN_BIT, %f0 + fstox %f0, %f4 + movstouw %f4, %o0 + retl + movstouw %f5, %o1 +END (__llrintf_vis3) diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrintf.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrintf.S new file mode 100644 index 0000000000..f2236f0eec --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrintf.S @@ -0,0 +1,51 @@ +#include <sysdep.h> + + .text +ENTRY(__llrintf) + .type __llrintf, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__llrintf_vis3), %o1 + xor %o1, %gdop_lox10(__llrintf_vis3), %o1 +# else + set __llrintf_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__llrintf_generic), %o1 + xor %o1, %gdop_lox10(__llrintf_generic), %o1 +# else + set __llrintf_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__llrintf) +weak_alias (__llrintf, llrintf) + +strong_alias (__llrintf, __lllrintf) +weak_alias (__lllrintf, lllrintf) + +# undef weak_alias +# define weak_alias(a, b) +# undef strong_alias +# define strong_alias(a, b) + +#define __llrintf __llrintf_generic + +#include "../s_llrintf.S" diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rint-vis3.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rint-vis3.S new file mode 100644 index 0000000000..6c4a3e00dd --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rint-vis3.S @@ -0,0 +1,55 @@ +/* Round float to int floating-point values, sparc32 v9 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__rint_vis3) + sethi %hi(TWO_FIFTYTWO), %o2 + sllx %o0, 32, %o0 + + or %o0, %o1, %o0 + fzero ZERO + + movxtod %o0, %f0 + sllx %o2, 32, %o2 + fnegd ZERO, SIGN_BIT + + movxtod %o2, %f16 + fabsd %f0, %f14 + + fcmpd %fcc3, %f14, %f16 + + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + + for %f16, SIGN_BIT, %f16 + faddd %f0, %f16, %f6 + fsubd %f6, %f16, %f0 + fabsd %f0, %f0 + retl + for %f0, SIGN_BIT, %f0 +END (__rint_vis3) diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rint.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rint.S new file mode 100644 index 0000000000..3872ae299e --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rint.S @@ -0,0 +1,46 @@ +#include <sysdep.h> + + .text +ENTRY(__rint) + .type __rint, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__rint_vis3), %o1 + xor %o1, %gdop_lox10(__rint_vis3), %o1 +# else + set __rint_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__rint_generic), %o1 + xor %o1, %gdop_lox10(__rint_generic), %o1 +# else + set __rint_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__rint) +weak_alias (__rint, rint) + +# undef weak_alias +# define weak_alias(a, b) + +#define __rint __rint_generic + +#include "../s_rint.S" diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rintf-vis3.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rintf-vis3.S new file mode 100644 index 0000000000..ec0bb37b13 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rintf-vis3.S @@ -0,0 +1,51 @@ +/* Round float to int floating-point values, sparc32 v9 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__rintf_vis3) + movwtos %o0, %f1 + sethi %hi(TWO_TWENTYTHREE), %o2 + fzeros ZERO + + fnegs ZERO, SIGN_BIT + + movwtos %o2, %f16 + fabss %f1, %f14 + + fcmps %fcc3, %f14, %f16 + + fmovsuge %fcc3, ZERO, %f16 + fands %f1, SIGN_BIT, SIGN_BIT + + fors %f16, SIGN_BIT, %f16 + fadds %f1, %f16, %f5 + fsubs %f5, %f16, %f0 + fabss %f0, %f0 + retl + fors %f0, SIGN_BIT, %f0 +END (__rintf_vis3) diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rintf.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rintf.S new file mode 100644 index 0000000000..9918929220 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rintf.S @@ -0,0 +1,46 @@ +#include <sysdep.h> + + .text +ENTRY(__rintf) + .type __rintf, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__rintf_vis3), %o1 + xor %o1, %gdop_lox10(__rintf_vis3), %o1 +# else + set __rintf_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__rintf_generic), %o1 + xor %o1, %gdop_lox10(__rintf_generic), %o1 +# else + set __rintf_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__rintf) +weak_alias (__rintf, rintf) + +# undef weak_alias +# define weak_alias(a, b) + +#define __rintf __rintf_generic + +#include "../s_rintf.S" diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrt-vis3.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrt-vis3.S new file mode 100644 index 0000000000..3880da0d8e --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrt-vis3.S @@ -0,0 +1,49 @@ +/* sqrt function. sparc32 v9 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__sqrt_vis3) + movwtos %o0, %f0 + fzero %f8 + movwtos %o1, %f1 + fcmpd %f0, %f8 + fbl 1f + nop +8: retl + fsqrtd %f0, %f0 +1: +#ifdef SHARED + SETUP_PIC_REG_LEAF(o5, g1) + sethi %gdop_hix22(_LIB_VERSION), %g1 + xor %g1, %gdop_lox10(_LIB_VERSION), %g1 + ld [%o5 + %g1], %g1, %gdop(_LIB_VERSION) +#else + sethi %hi(_LIB_VERSION), %g1 + or %g1, %lo(_LIB_VERSION), %g1 +#endif + ld [%g1], %g1 + cmp %g1, -1 + be 8b + mov %o0, %o2 + mov %o1, %o3 + mov 26, %o4 + mov %o7, %g1 + call __kernel_standard + mov %g1, %o7 +END (__sqrt_vis3) diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrt.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrt.S new file mode 100644 index 0000000000..80b15767ce --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrt.S @@ -0,0 +1,46 @@ +#include <sysdep.h> + + .text +ENTRY(__sqrt) + .type __sqrt, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__sqrt_vis3), %o1 + xor %o1, %gdop_lox10(__sqrt_vis3), %o1 +# else + set __sqrt_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__sqrt_generic), %o1 + xor %o1, %gdop_lox10(__sqrt_generic), %o1 +# else + set __sqrt_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__sqrt) +weak_alias (__sqrt, sqrt) + +# undef weak_alias +# define weak_alias(a, b) + +#define __sqrt __sqrt_generic + +#include "../w_sqrt.S" diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrtf-vis3.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrtf-vis3.S new file mode 100644 index 0000000000..2d4270f9cd --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrtf-vis3.S @@ -0,0 +1,47 @@ +/* sqrtf function. sparc32 v9 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__sqrtf_vis3) + movwtos %o0, %f0 + fzeros %f8 + fcmps %f0, %f8 + fbl 1f + nop +8: retl + fsqrts %f0, %f0 +1: +#ifdef SHARED + SETUP_PIC_REG_LEAF(o5, g1) + sethi %gdop_hix22(_LIB_VERSION), %g1 + xor %g1, %gdop_lox10(_LIB_VERSION), %g1 + ld [%o5 + %g1], %g1, %gdop(_LIB_VERSION) +#else + sethi %hi(_LIB_VERSION), %g1 + or %g1, %lo(_LIB_VERSION), %g1 +#endif + ld [%g1], %g1 + cmp %g1, -1 + be 8b + mov %o0, %o1 + mov 126, %o2 + mov %o7, %g1 + call __kernel_standard_f + mov %g1, %o7 +END (__sqrtf_vis3) diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrtf.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrtf.S new file mode 100644 index 0000000000..a700a4e876 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrtf.S @@ -0,0 +1,46 @@ +#include <sysdep.h> + + .text +ENTRY(__sqrtf) + .type __sqrtf, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__sqrtf_vis3), %o1 + xor %o1, %gdop_lox10(__sqrtf_vis3), %o1 +# else + set __sqrtf_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__sqrtf_generic), %o1 + xor %o1, %gdop_lox10(__sqrtf_generic), %o1 +# else + set __sqrtf_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__sqrtf) +weak_alias (__sqrtf, sqrtf) + +# undef weak_alias +# define weak_alias(a, b) + +#define __sqrtf __sqrtf_generic + +#include "../w_sqrtf.S" diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/unix/sysv/linux/multiarch/Implies b/sysdeps/sparc/sparc32/sparcv9/fpu/unix/sysv/linux/multiarch/Implies new file mode 100644 index 0000000000..a380d8a739 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/unix/sysv/linux/multiarch/Implies @@ -0,0 +1,4 @@ +# We must list this here to move it ahead of the ldbl-opt code. +sparc/sparc32/sparcv9/fpu/multiarch +sparc/sparc32/sparcv9/fpu +sparc/sparc32/fpu diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/Makefile b/sysdeps/sparc/sparc64/fpu/multiarch/Makefile index b03884de0d..564ed26c3d 100644 --- a/sysdeps/sparc/sparc64/fpu/multiarch/Makefile +++ b/sysdeps/sparc/sparc64/fpu/multiarch/Makefile @@ -1,9 +1,13 @@ ifeq ($(subdir),math) ifeq ($(have-as-vis3),yes) -libm-sysdep_routines += m_signbitf-vis3 m_signbit-vis3 -sysdep_routines += s_signbitf-vis3 s_signbit-vis3 - -CFLAGS-s_signbitf-vis3.S = -Wa,-Av9d -CFLAGS-s_signbit-vis3.S = -Wa,-Av9d +libm-sysdep_routines += m_signbitf-vis3 m_signbit-vis3 s_ceilf-vis3 \ + s_ceil-vis3 m_finitef-vis3 m_finite-vis3 \ + s_floorf-vis3 s_floor-vis3 m_isinff-vis3 \ + m_isinf-vis3 m_isnanf-vis3 m_isnan-vis3 \ + s_lrintf-vis3 s_lrint-vis3 s_rintf-vis3 \ + s_rint-vis3 +sysdep_routines += s_signbitf-vis3 s_signbit-vis3 s_finitef-vis3 \ + s_finite-vis3 s_isinff-vis3 s_isinf-vis3 \ + s_isnanf-vis3 s_isnan-vis3 +endif endif -endif \ No newline at end of file diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_ceil-vis3.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_ceil-vis3.S new file mode 100644 index 0000000000..ebf9d80b89 --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_ceil-vis3.S @@ -0,0 +1,75 @@ +/* ceil function, sparc64 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* Since changing the rounding mode is extremely expensive, we + try to round up using a method that is rounding mode + agnostic. + + We add then subtract (or subtract than add if the initial + value was negative) 2**23 to the value, then subtract it + back out. + + This will clear out the fractional portion of the value. + One of two things will happen for non-whole initial values. + Either the rounding mode will round it up, or it will be + rounded down. If the value started out whole, it will be + equal after the addition and subtraction. This means we + can accurately detect with one test whether we need to add + another 1.0 to round it up properly. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ +#define ONE_DOT_ZERO 0x3ff00000 /* 1.0 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__ceil_vis3) + sethi %hi(TWO_FIFTYTWO), %o2 + sethi %hi(ONE_DOT_ZERO), %o3 + fzero ZERO + + sllx %o2, 32, %o2 + fnegd ZERO, SIGN_BIT + + sllx %o3, 32, %o3 + movxtod %o2, %f16 + fabsd %f0, %f14 + + fcmpd %fcc3, %f14, %f16 + + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + + for %f16, SIGN_BIT, %f16 + faddd %f0, %f16, %f18 + fsubd %f18, %f16, %f18 + fcmpd %fcc2, %f18, %f0 + movxtod %o3, %f20 + + fmovduge %fcc2, ZERO, %f20 + faddd %f18, %f20, %f0 + fabsd %f0, %f0 + retl + for %f0, SIGN_BIT, %f0 +END (__ceil_vis3) diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_ceil.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_ceil.S new file mode 100644 index 0000000000..f91fda61b9 --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_ceil.S @@ -0,0 +1,46 @@ +#include <sysdep.h> + + .text +ENTRY(__ceil) + .type __ceil, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__ceil_vis3), %o1 + xor %o1, %gdop_lox10(__ceil_vis3), %o1 +# else + set __ceil_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__ceil_generic), %o1 + xor %o1, %gdop_lox10(__ceil_generic), %o1 +# else + set __ceil_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__ceil) +weak_alias (__ceil, ceil) + +# undef weak_alias +# define weak_alias(a, b) + +#define __ceil __ceil_generic + +#include "../s_ceil.S" diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf-vis3.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf-vis3.S new file mode 100644 index 0000000000..09d2d3dbe3 --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf-vis3.S @@ -0,0 +1,73 @@ +/* Float ceil function, sparc64 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* Since changing the rounding mode is extremely expensive, we + try to round up using a method that is rounding mode + agnostic. + + We add then subtract (or subtract than add if the initial + value was negative) 2**23 to the value, then subtract it + back out. + + This will clear out the fractional portion of the value. + One of two things will happen for non-whole initial values. + Either the rounding mode will round it up, or it will be + rounded down. If the value started out whole, it will be + equal after the addition and subtraction. This means we + can accurately detect with one test whether we need to add + another 1.0 to round it up properly. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ +#define ONE_DOT_ZERO 0x3f800000 /* 1.0 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__ceilf_vis3) + sethi %hi(TWO_TWENTYTHREE), %o2 + sethi %hi(ONE_DOT_ZERO), %o3 + fzeros ZERO + + fnegs ZERO, SIGN_BIT + + movwtos %o2, %f16 + fabss %f1, %f14 + + fcmps %fcc3, %f14, %f16 + + fmovsuge %fcc3, ZERO, %f16 + fands %f1, SIGN_BIT, SIGN_BIT + + fors %f16, SIGN_BIT, %f16 + fadds %f1, %f16, %f5 + fsubs %f5, %f16, %f5 + fcmps %fcc2, %f5, %f1 + movwtos %o3, %f9 + + fmovsuge %fcc2, ZERO, %f9 + fadds %f5, %f9, %f0 + fabss %f0, %f0 + retl + fors %f0, SIGN_BIT, %f0 +END (__ceilf_vis3) diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf.S new file mode 100644 index 0000000000..048b6195d8 --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf.S @@ -0,0 +1,46 @@ +#include <sysdep.h> + + .text +ENTRY(__ceilf) + .type __ceilf, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__ceilf_vis3), %o1 + xor %o1, %gdop_lox10(__ceilf_vis3), %o1 +# else + set __ceilf_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__ceilf_generic), %o1 + xor %o1, %gdop_lox10(__ceilf_generic), %o1 +# else + set __ceilf_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__ceilf) +weak_alias (__ceilf, ceilf) + +# undef weak_alias +# define weak_alias(a, b) + +#define __ceilf __ceilf_generic + +#include "../s_ceilf.S" diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_finite-vis3.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_finite-vis3.S new file mode 100644 index 0000000000..6929b56ba2 --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_finite-vis3.S @@ -0,0 +1,28 @@ +/* finite(). sparc64 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__finite_vis3) + fabsd %f0, %f0 + movstouw %f0, %o0 + sethi %hi(0x7ff00000), %o2 + sub %o0, %o2, %o0 + retl + srl %o0, 31, %o0 +END (__finite_vis3) diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_finite.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_finite.S new file mode 100644 index 0000000000..f4bfdcef96 --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_finite.S @@ -0,0 +1,49 @@ +#include <sysdep.h> + + .text +ENTRY(__finite) + .type __finite, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__finite_vis3), %o1 + xor %o1, %gdop_lox10(__finite_vis3), %o1 +# else + set __finite_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__finite_generic), %o1 + xor %o1, %gdop_lox10(__finite_generic), %o1 +# else + set __finite_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__finite) +hidden_def (__finite) +weak_alias (__finite, finite) + +# undef weak_alias +# define weak_alias(a, b) +# undef hidden_def +# define hidden_def(a) + +#define __finite __finite_generic + +#include "../s_finite.S" diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_finitef-vis3.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_finitef-vis3.S new file mode 100644 index 0000000000..93420ff6a7 --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_finitef-vis3.S @@ -0,0 +1,28 @@ +/* finitef(). sparc64 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__finitef_vis3) + fabss %f1, %f0 + movstouw %f0, %o0 + sethi %hi(0x7f800000), %o2 + sub %o0, %o2, %o0 + retl + srl %o0, 31, %o0 +END (__finitef_vis3) diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_finitef.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_finitef.S new file mode 100644 index 0000000000..65ca7fd1c6 --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_finitef.S @@ -0,0 +1,49 @@ +#include <sysdep.h> + + .text +ENTRY(__finitef) + .type __finitef, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__finitef_vis3), %o1 + xor %o1, %gdop_lox10(__finitef_vis3), %o1 +# else + set __finitef_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__finitef_generic), %o1 + xor %o1, %gdop_lox10(__finitef_generic), %o1 +# else + set __finitef_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__finitef) +hidden_def (__finitef) +weak_alias (__finitef, finitef) + +# undef weak_alias +# define weak_alias(a, b) +# undef hidden_def +# define hidden_def(a) + +#define __finitef __finitef_generic + +#include "../s_finitef.S" diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_floor-vis3.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_floor-vis3.S new file mode 100644 index 0000000000..86ed1ae92b --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_floor-vis3.S @@ -0,0 +1,75 @@ +/* floor function, sparc64 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* Since changing the rounding mode is extremely expensive, we + try to round up using a method that is rounding mode + agnostic. + + We add then subtract (or subtract than add if the initial + value was negative) 2**23 to the value, then subtract it + back out. + + This will clear out the fractional portion of the value. + One of two things will happen for non-whole initial values. + Either the rounding mode will round it up, or it will be + rounded down. If the value started out whole, it will be + equal after the addition and subtraction. This means we + can accurately detect with one test whether we need to add + another 1.0 to round it up properly. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ +#define ONE_DOT_ZERO 0x3ff00000 /* 1.0 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__floor_vis3) + sethi %hi(TWO_FIFTYTWO), %o2 + sethi %hi(ONE_DOT_ZERO), %o3 + fzero ZERO + + sllx %o2, 32, %o2 + fnegd ZERO, SIGN_BIT + + sllx %o3, 32, %o3 + movxtod %o2, %f16 + fabsd %f0, %f14 + + fcmpd %fcc3, %f14, %f16 + + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + + for %f16, SIGN_BIT, %f16 + faddd %f0, %f16, %f18 + fsubd %f18, %f16, %f18 + fcmpd %fcc2, %f18, %f0 + movxtod %o3, %f20 + + fmovdule %fcc2, ZERO, %f20 + fsubd %f18, %f20, %f0 + fabsd %f0, %f0 + retl + for %f0, SIGN_BIT, %f0 +END (__floor_vis3) diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_floor.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_floor.S new file mode 100644 index 0000000000..1cdc53fb84 --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_floor.S @@ -0,0 +1,46 @@ +#include <sysdep.h> + + .text +ENTRY(__floor) + .type __floor, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__floor_vis3), %o1 + xor %o1, %gdop_lox10(__floor_vis3), %o1 +# else + set __floor_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__floor_generic), %o1 + xor %o1, %gdop_lox10(__floor_generic), %o1 +# else + set __floor_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__floor) +weak_alias (__floor, floor) + +# undef weak_alias +# define weak_alias(a, b) + +#define __floor __floor_generic + +#include "../s_floor.S" diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_floorf-vis3.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_floorf-vis3.S new file mode 100644 index 0000000000..b663b64753 --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_floorf-vis3.S @@ -0,0 +1,73 @@ +/* Float floor function, sparc64 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* Since changing the rounding mode is extremely expensive, we + try to round up using a method that is rounding mode + agnostic. + + We add then subtract (or subtract than add if the initial + value was negative) 2**23 to the value, then subtract it + back out. + + This will clear out the fractional portion of the value. + One of two things will happen for non-whole initial values. + Either the rounding mode will round it up, or it will be + rounded down. If the value started out whole, it will be + equal after the addition and subtraction. This means we + can accurately detect with one test whether we need to add + another 1.0 to round it up properly. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ +#define ONE_DOT_ZERO 0x3f800000 /* 1.0 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__floorf_vis3) + sethi %hi(TWO_TWENTYTHREE), %o2 + sethi %hi(ONE_DOT_ZERO), %o3 + fzeros ZERO + + fnegs ZERO, SIGN_BIT + + movwtos %o2, %f16 + fabss %f1, %f14 + + fcmps %fcc3, %f14, %f16 + + fmovsuge %fcc3, ZERO, %f16 + fands %f1, SIGN_BIT, SIGN_BIT + + fors %f16, SIGN_BIT, %f16 + fadds %f1, %f16, %f5 + fsubs %f5, %f16, %f5 + fcmps %fcc2, %f5, %f1 + movwtos %o3, %f9 + + fmovsule %fcc2, ZERO, %f9 + fsubs %f5, %f9, %f0 + fabss %f0, %f0 + retl + fors %f0, SIGN_BIT, %f0 +END (__floorf_vis3) diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_floorf.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_floorf.S new file mode 100644 index 0000000000..0dcd0e1431 --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_floorf.S @@ -0,0 +1,46 @@ +#include <sysdep.h> + + .text +ENTRY(__floorf) + .type __floorf, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__floorf_vis3), %o1 + xor %o1, %gdop_lox10(__floorf_vis3), %o1 +# else + set __floorf_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__floorf_generic), %o1 + xor %o1, %gdop_lox10(__floorf_generic), %o1 +# else + set __floorf_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__floorf) +weak_alias (__floorf, floorf) + +# undef weak_alias +# define weak_alias(a, b) + +#define __floorf __floorf_generic + +#include "../s_floorf.S" diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_isinf-vis3.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_isinf-vis3.S new file mode 100644 index 0000000000..7f7cd5ee69 --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_isinf-vis3.S @@ -0,0 +1,31 @@ +/* isinf(). sparc64 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__isinf_vis3) + movdtox %f0, %g1 + sethi %hi(0x7ff00000), %o2 + sllx %o2, 32, %o2 + sllx %g1, 1, %o4 + srlx %o4, 1, %o5 + srax %g1, 62, %o0 + xor %o5, %o2, %o3 + retl + movrne %o3, %g0, %o0 +END (__isinf_vis3) diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_isinf.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_isinf.S new file mode 100644 index 0000000000..8b47267f6b --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_isinf.S @@ -0,0 +1,49 @@ +#include <sysdep.h> + + .text +ENTRY(__isinf) + .type __isinf, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__isinf_vis3), %o1 + xor %o1, %gdop_lox10(__isinf_vis3), %o1 +# else + set __isinf_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__isinf_generic), %o1 + xor %o1, %gdop_lox10(__isinf_generic), %o1 +# else + set __isinf_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__isinf) +hidden_def (__isinf) +weak_alias (__isinf, isinf) + +# undef weak_alias +# define weak_alias(a, b) +# undef hidden_def +# define hidden_def(a) + +#define __isinf __isinf_generic + +#include "../s_isinf.S" diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_isinff-vis3.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_isinff-vis3.S new file mode 100644 index 0000000000..7d59d5db3f --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_isinff-vis3.S @@ -0,0 +1,30 @@ +/* isinff(). sparc64 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__isinff_vis3) + movstouw %f1, %g1 + sethi %hi(0x7f800000), %o2 + sll %g1, 1, %o4 + srl %o4, 1, %o5 + sra %g1, 30, %o0 + xor %o5, %o2, %o3 + retl + movrne %o3, %g0, %o0 +END (__isinff_vis3) diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_isinff.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_isinff.S new file mode 100644 index 0000000000..9a42a01d40 --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_isinff.S @@ -0,0 +1,49 @@ +#include <sysdep.h> + + .text +ENTRY(__isinff) + .type __isinff, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__isinff_vis3), %o1 + xor %o1, %gdop_lox10(__isinff_vis3), %o1 +# else + set __isinff_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__isinff_generic), %o1 + xor %o1, %gdop_lox10(__isinff_generic), %o1 +# else + set __isinff_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__isinff) +hidden_def (__isinff) +weak_alias (__isinff, isinff) + +# undef weak_alias +# define weak_alias(a, b) +# undef hidden_def +# define hidden_def(a) + +#define __isinff __isinff_generic + +#include "../s_isinff.S" diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_isnan-vis3.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_isnan-vis3.S new file mode 100644 index 0000000000..b3b1014443 --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_isnan-vis3.S @@ -0,0 +1,30 @@ +/* isnan(). sparc64 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__isnan_vis3) + movdtox %f0, %o0 + sethi %hi(0x7ff00000), %g1 + sllx %g1, 32, %g1 + sllx %o0, 1, %o0 + srlx %o0, 1, %o0 + sub %g1, %o0, %o0 + retl + srlx %o0, 63, %o0 +END (__isnan_vis3) diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_isnan.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_isnan.S new file mode 100644 index 0000000000..d75077cfec --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_isnan.S @@ -0,0 +1,49 @@ +#include <sysdep.h> + + .text +ENTRY(__isnan) + .type __isnan, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__isnan_vis3), %o1 + xor %o1, %gdop_lox10(__isnan_vis3), %o1 +# else + set __isnan_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__isnan_generic), %o1 + xor %o1, %gdop_lox10(__isnan_generic), %o1 +# else + set __isnan_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__isnan) +hidden_def (__isnan) +weak_alias (__isnan, isnan) + +# undef weak_alias +# define weak_alias(a, b) +# undef hidden_def +# define hidden_def(a) + +#define __isnan __isnan_generic + +#include "../s_isnan.S" diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_isnanf-vis3.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_isnanf-vis3.S new file mode 100644 index 0000000000..cd60d3e563 --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_isnanf-vis3.S @@ -0,0 +1,29 @@ +/* isnanf(). sparc64 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + +ENTRY (__isnanf_vis3) + movstouw %f1, %o0 + sethi %hi(0x7f800000), %g1 + sll %o0, 1, %o0 + srl %o0, 1, %o0 + sub %g1, %o0, %o0 + retl + srl %o0, 31, %o0 +END (__isnanf_vis3) diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_isnanf.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_isnanf.S new file mode 100644 index 0000000000..6d11dd4b4e --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_isnanf.S @@ -0,0 +1,49 @@ +#include <sysdep.h> + + .text +ENTRY(__isnanf) + .type __isnanf, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__isnanf_vis3), %o1 + xor %o1, %gdop_lox10(__isnanf_vis3), %o1 +# else + set __isnanf_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__isnanf_generic), %o1 + xor %o1, %gdop_lox10(__isnanf_generic), %o1 +# else + set __isnanf_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__isnanf) +hidden_def (__isnanf) +weak_alias (__isnanf, isnanf) + +# undef weak_alias +# define weak_alias(a, b) +# undef hidden_def +# define hidden_def(a) + +#define __isnanf __isnanf_generic + +#include "../s_isnanf.S" diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_lrint-vis3.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_lrint-vis3.S new file mode 100644 index 0000000000..4633017fc5 --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_lrint-vis3.S @@ -0,0 +1,52 @@ +/* lrint(), sparc64 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__lrint_vis3) + sethi %hi(TWO_FIFTYTWO), %o2 + sllx %o2, 32, %o2 + fzero ZERO + + fnegd ZERO, SIGN_BIT + movxtod %o2, %f16 + fabsd %f0, %f14 + + fcmpd %fcc3, %f14, %f16 + + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + + for %f16, SIGN_BIT, %f16 + faddd %f0, %f16, %f6 + fsubd %f6, %f16, %f0 + fabsd %f0, %f0 + for %f0, SIGN_BIT, %f0 + fdtox %f0, %f4 + retl + movdtox %f4, %o0 +END (__lrint_vis3) diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_lrint.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_lrint.S new file mode 100644 index 0000000000..e63e83343b --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_lrint.S @@ -0,0 +1,51 @@ +#include <sysdep.h> + + .text +ENTRY(__lrint) + .type __lrint, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__lrint_vis3), %o1 + xor %o1, %gdop_lox10(__lrint_vis3), %o1 +# else + set __lrint_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__lrint_generic), %o1 + xor %o1, %gdop_lox10(__lrint_generic), %o1 +# else + set __lrint_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__lrint) +weak_alias (__lrint, lrint) + +strong_alias (__lrint, __llrint) +weak_alias (__llrint, llrint) + +# undef weak_alias +# define weak_alias(a, b) +# undef strong_alias +# define strong_alias(a, b) + +#define __lrint __lrint_generic + +#include "../s_lrint.S" diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_lrintf-vis3.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_lrintf-vis3.S new file mode 100644 index 0000000000..6358732f12 --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_lrintf-vis3.S @@ -0,0 +1,51 @@ +/* lrintf(), sparc64 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__lrintf_vis3) + sethi %hi(TWO_TWENTYTHREE), %o2 + fzeros ZERO + + fnegs ZERO, SIGN_BIT + movwtos %o2, %f16 + fabss %f1, %f14 + + fcmps %fcc3, %f14, %f16 + + fmovsuge %fcc3, ZERO, %f16 + fands %f1, SIGN_BIT, SIGN_BIT + + fors %f16, SIGN_BIT, %f16 + fadds %f1, %f16, %f5 + fsubs %f5, %f16, %f0 + fabss %f0, %f0 + fors %f0, SIGN_BIT, %f0 + fstox %f0, %f4 + retl + movdtox %f4, %o0 +END (__lrintf_vis3) diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_lrintf.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_lrintf.S new file mode 100644 index 0000000000..809aaa8a14 --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_lrintf.S @@ -0,0 +1,51 @@ +#include <sysdep.h> + + .text +ENTRY(__lrintf) + .type __lrintf, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__lrintf_vis3), %o1 + xor %o1, %gdop_lox10(__lrintf_vis3), %o1 +# else + set __lrintf_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__lrintf_generic), %o1 + xor %o1, %gdop_lox10(__lrintf_generic), %o1 +# else + set __lrintf_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__lrintf) +weak_alias (__lrintf, lrintf) + +strong_alias (__lrintf, __llrintf) +weak_alias (__llrintf, llrintf) + +# undef weak_alias +# define weak_alias(a, b) +# undef strong_alias +# define strong_alias(a, b) + +#define __lrintf __lrintf_generic + +#include "../s_lrintf.S" diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_rint-vis3.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_rint-vis3.S new file mode 100644 index 0000000000..d4fcd19d9b --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_rint-vis3.S @@ -0,0 +1,50 @@ +/* Round float to int floating-point values, sparc64 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__rint_vis3) + sethi %hi(TWO_FIFTYTWO), %o2 + sllx %o2, 32, %o2 + fzero ZERO + + fnegd ZERO, SIGN_BIT + movxtod %o2, %f16 + fabsd %f0, %f14 + + fcmpd %fcc3, %f14, %f16 + + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + + for %f16, SIGN_BIT, %f16 + faddd %f0, %f16, %f6 + fsubd %f6, %f16, %f0 + fabsd %f0, %f0 + retl + for %f0, SIGN_BIT, %f0 +END (__rint_vis3) diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_rint.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_rint.S new file mode 100644 index 0000000000..3872ae299e --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_rint.S @@ -0,0 +1,46 @@ +#include <sysdep.h> + + .text +ENTRY(__rint) + .type __rint, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__rint_vis3), %o1 + xor %o1, %gdop_lox10(__rint_vis3), %o1 +# else + set __rint_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__rint_generic), %o1 + xor %o1, %gdop_lox10(__rint_generic), %o1 +# else + set __rint_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__rint) +weak_alias (__rint, rint) + +# undef weak_alias +# define weak_alias(a, b) + +#define __rint __rint_generic + +#include "../s_rint.S" diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_rintf-vis3.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_rintf-vis3.S new file mode 100644 index 0000000000..ea640589e4 --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_rintf-vis3.S @@ -0,0 +1,49 @@ +/* Round float to int floating-point values, sparc64 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller <davem@davemloft.net>, 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#include <sysdep.h> + + /* VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__rintf_vis3) + sethi %hi(TWO_TWENTYTHREE), %o2 + fzeros ZERO + + fnegs ZERO, SIGN_BIT + movwtos %o2, %f16 + fabss %f1, %f14 + + fcmps %fcc3, %f14, %f16 + + fmovsuge %fcc3, ZERO, %f16 + fands %f1, SIGN_BIT, SIGN_BIT + + fors %f16, SIGN_BIT, %f16 + fadds %f1, %f16, %f5 + fsubs %f5, %f16, %f0 + fabss %f0, %f0 + retl + fors %f0, SIGN_BIT, %f0 +END (__rintf_vis3) diff --git a/sysdeps/sparc/sparc64/fpu/multiarch/s_rintf.S b/sysdeps/sparc/sparc64/fpu/multiarch/s_rintf.S new file mode 100644 index 0000000000..9918929220 --- /dev/null +++ b/sysdeps/sparc/sparc64/fpu/multiarch/s_rintf.S @@ -0,0 +1,46 @@ +#include <sysdep.h> + + .text +ENTRY(__rintf) + .type __rintf, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__rintf_vis3), %o1 + xor %o1, %gdop_lox10(__rintf_vis3), %o1 +# else + set __rintf_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__rintf_generic), %o1 + xor %o1, %gdop_lox10(__rintf_generic), %o1 +# else + set __rintf_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__rintf) +weak_alias (__rintf, rintf) + +# undef weak_alias +# define weak_alias(a, b) + +#define __rintf __rintf_generic + +#include "../s_rintf.S" |