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| author | Marcus Shawcroft <marcus.shawcroft@linaro.org> | 2012-11-07 13:32:08 +0000 |
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| committer | Marcus Shawcroft <marcus.shawcroft@linaro.org> | 2012-11-07 13:32:08 +0000 |
| commit | 19b2ecfcae9ccd7f9a974e8d1869d45ecd7310bb (patch) | |
| tree | 20ce69e71f95879d75e8d8c4cf5590ebace360f2 | |
| parent | 60e235ee2ae834bb9f7a884f1b192304b9fdcf33 (diff) | |
| download | glibc-19b2ecfcae9ccd7f9a974e8d1869d45ecd7310bb.tar.gz glibc-19b2ecfcae9ccd7f9a974e8d1869d45ecd7310bb.tar.xz glibc-19b2ecfcae9ccd7f9a974e8d1869d45ecd7310bb.zip | |
Adding AArch64 support to elf/elf.h
| -rw-r--r-- | ChangeLog | 12 | ||||
| -rw-r--r-- | elf/elf.h | 18 |
2 files changed, 30 insertions, 0 deletions
diff --git a/ChangeLog b/ChangeLog index aeebbc462c..69593dec0e 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,15 @@ +2012-11-07 Marcus Shawcroft <marcus.shawcroft@linaro.org> + + * elf/elf.h (EM_AARCH64): New macro. + (R_AARCH64_NONE, R_AARCH64_ABS64, R_AARCH64_ABS32): Likewise. + (R_AARCH64_COPY, R_AARCH64_GLOB_DAT, R_AARCH64_JUMP_SLOT): Likewise. + (R_AARCH64_RELATIVE, R_AARCH64_TLS_DTPMOD64): Likewise. + (R_AARCH64_TLS_DTPREL64, R_AARCH64_TLS_TPREL64): Likewise. + (R_AARCH64_TLSDESC): Likewise. + (NT_ARM_TLS): Likewise. + (NT_ARM_HW_BREAK): Likewise. + (NT_ARM_HW_WATCH): Likewise. + 2012-11-07 Joseph Myers <joseph@codesourcery.com> [BZ #14811] diff --git a/elf/elf.h b/elf/elf.h index 25249246bc..5a9b13fdcb 100644 --- a/elf/elf.h +++ b/elf/elf.h @@ -249,6 +249,7 @@ typedef struct #define EM_OPENRISC 92 /* OpenRISC 32-bit embedded processor */ #define EM_ARC_A5 93 /* ARC Cores Tangent-A5 */ #define EM_XTENSA 94 /* Tensilica Xtensa Architecture */ +#define EM_AARCH64 183 /* ARM AARCH64 */ #define EM_TILEPRO 188 /* Tilera TILEPro */ #define EM_TILEGX 191 /* Tilera TILE-Gx */ #define EM_NUM 192 @@ -631,6 +632,9 @@ typedef struct #define NT_S390_LAST_BREAK 0x306 /* s390 breaking event address */ #define NT_S390_SYSTEM_CALL 0x307 /* s390 system call restart data */ #define NT_ARM_VFP 0x400 /* ARM VFP/NEON registers */ +#define NT_ARM_TLS 0x401 /* ARM TLS register */ +#define NT_ARM_HW_BREAK 0x402 /* ARM hardware breakpoint registers */ +#define NT_ARM_HW_WATCH 0x403 /* ARM hardware watchpoint registers */ /* Legal values for the note segment descriptor types for object files. */ @@ -2306,6 +2310,20 @@ typedef Elf32_Addr Elf32_Conflict; #define SHT_ARM_ATTRIBUTES (SHT_LOPROC + 3) /* ARM attributes section. */ +/* AArch64 specific declarations. */ + +#define R_AARCH64_NONE 0 /* No relocation. */ +#define R_AARCH64_ABS64 257 /* Direct 64 bit. */ +#define R_AARCH64_ABS32 258 /* Direct 32 bit. */ +#define R_AARCH64_COPY 1024 /* Copy symbol at runtime. */ +#define R_AARCH64_GLOB_DAT 1025 /* Create GOT entry. */ +#define R_AARCH64_JUMP_SLOT 1026 /* Create PLT entry. */ +#define R_AARCH64_RELATIVE 1027 /* Adjust by program base. */ +#define R_AARCH64_TLS_DTPMOD64 1028 /* Module number, 64 bit. */ +#define R_AARCH64_TLS_DTPREL64 1029 /* Module-relative offset, 64 bit. */ +#define R_AARCH64_TLS_TPREL64 1030 /* TP-relative offset, 64 bit. */ +#define R_AARCH64_TLSDESC 1031 /* TLS Descriptor. */ + /* ARM relocs. */ #define R_ARM_NONE 0 /* No reloc */ |