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| author | Wilco Dijkstra <wdijkstr@arm.com> | 2014-12-22 17:11:18 +0000 |
|---|---|---|
| committer | Wilco Dijkstra <wdijkstr@arm.com> | 2014-12-22 17:14:55 +0000 |
| commit | 8622d5568841458e801f8dd82846c5ba7e415f3e (patch) | |
| tree | 004e03ed83e48e0274a831f66c4e30f3b4c2642f | |
| parent | f3806bdbc1d98c3392273837fcab86147212149d (diff) | |
| download | glibc-8622d5568841458e801f8dd82846c5ba7e415f3e.tar.gz glibc-8622d5568841458e801f8dd82846c5ba7e415f3e.tar.xz glibc-8622d5568841458e801f8dd82846c5ba7e415f3e.zip | |
Optimize to avoid an unnecessary FPCR read.
| -rw-r--r-- | ChangeLog | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/ChangeLog b/ChangeLog index c8db220517..708f8a962a 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,5 +1,10 @@ 2014-12-22 Wilco Dijkstra <wdijkstr@arm.com> + * sysdeps/aarch64/fpu/feenablxcpt.c (feenableexcept): + Optimize to avoid an unnecessary FPCR read. + +2014-12-22 Wilco Dijkstra <wdijkstr@arm.com> + * sysdeps/aarch64/fpu/fesetenv.c (fesetenv): Optimize to reduce FPCR/FPSR accesses. |