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| author | H.J. Lu <hjl.tools@gmail.com> | 2018-05-21 16:54:46 -0700 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2018-05-21 16:54:59 -0700 |
| commit | e28e9b1ec40d5b545d980b0a36cbe41f3d1dbf6a (patch) | |
| tree | 7fe0767441c477a36fe4d7aeb2caf17e7c45c18a | |
| parent | 1af30adcd59fae929371d3a56b239861b1088a6e (diff) | |
| download | glibc-e28e9b1ec40d5b545d980b0a36cbe41f3d1dbf6a.tar.gz glibc-e28e9b1ec40d5b545d980b0a36cbe41f3d1dbf6a.tar.xz glibc-e28e9b1ec40d5b545d980b0a36cbe41f3d1dbf6a.zip | |
x86-64: Check Prefer_FSRM in ifunc-memmove.h
Although the REP MOVSB implementations of memmove, memcpy and mempcpy aren't used by the current processors, this patch adds Prefer_FSRM check in ifunc-memmove.h so that they can be used in the future. * sysdeps/x86/cpu-features.h (bit_arch_Prefer_FSRM): New. (index_arch_Prefer_FSRM): Likewise. * sysdeps/x86/cpu-tunables.c (TUNABLE_CALLBACK (set_hwcaps)): Also check Prefer_FSRM. * sysdeps/x86_64/multiarch/ifunc-memmove.h (IFUNC_SELECTOR): Also return OPTIMIZE (erms) for Prefer_FSRM.
| -rw-r--r-- | ChangeLog | 9 | ||||
| -rw-r--r-- | sysdeps/x86/cpu-features.h | 2 | ||||
| -rw-r--r-- | sysdeps/x86/cpu-tunables.c | 2 | ||||
| -rw-r--r-- | sysdeps/x86_64/multiarch/ifunc-memmove.h | 3 |
4 files changed, 15 insertions, 1 deletions
diff --git a/ChangeLog b/ChangeLog index c8ff9d45c8..ee8f745229 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,5 +1,14 @@ 2018-05-21 H.J. Lu <hongjiu.lu@intel.com> + * sysdeps/x86/cpu-features.h (bit_arch_Prefer_FSRM): New. + (index_arch_Prefer_FSRM): Likewise. + * sysdeps/x86/cpu-tunables.c (TUNABLE_CALLBACK (set_hwcaps)): + Also check Prefer_FSRM. + * sysdeps/x86_64/multiarch/ifunc-memmove.h (IFUNC_SELECTOR): + Also return OPTIMIZE (erms) for Prefer_FSRM. + +2018-05-21 H.J. Lu <hongjiu.lu@intel.com> + * sysdeps/x86/cpu-features.h (bit_cpu_FSRM): New. (index_cpu_FSRM): Likewise. (reg_FSRM): Likewise. diff --git a/sysdeps/x86/cpu-features.h b/sysdeps/x86/cpu-features.h index 2088bd73ee..624e681e96 100644 --- a/sysdeps/x86/cpu-features.h +++ b/sysdeps/x86/cpu-features.h @@ -40,6 +40,7 @@ #define bit_arch_Prefer_No_AVX512 (1 << 20) #define bit_arch_MathVec_Prefer_No_AVX512 (1 << 21) #define bit_arch_XSAVEC_Usable (1 << 22) +#define bit_arch_Prefer_FSRM (1 << 23) /* CPUID Feature flags. */ @@ -264,6 +265,7 @@ extern const struct cpu_features *__get_cpu_features (void) # define index_arch_Prefer_No_AVX512 FEATURE_INDEX_1 # define index_arch_MathVec_Prefer_No_AVX512 FEATURE_INDEX_1 # define index_arch_XSAVEC_Usable FEATURE_INDEX_1 +# define index_arch_Prefer_FSRM FEATURE_INDEX_1 #endif /* !__ASSEMBLER__ */ diff --git a/sysdeps/x86/cpu-tunables.c b/sysdeps/x86/cpu-tunables.c index a21a615ec2..af761dcbbc 100644 --- a/sysdeps/x86/cpu-tunables.c +++ b/sysdeps/x86/cpu-tunables.c @@ -241,6 +241,8 @@ TUNABLE_CALLBACK (set_hwcaps) (tunable_val_t *valp) CHECK_GLIBC_IFUNC_ARCH_NEED_CPU_BOTH (n, cpu_features, Slow_SSE4_2, SSE4_2, disable, 11); + CHECK_GLIBC_IFUNC_ARCH_BOTH (n, cpu_features, Prefer_FSRM, + disable, 11); break; case 13: if (disable) diff --git a/sysdeps/x86_64/multiarch/ifunc-memmove.h b/sysdeps/x86_64/multiarch/ifunc-memmove.h index a2ffba0531..5b1eb1c92c 100644 --- a/sysdeps/x86_64/multiarch/ifunc-memmove.h +++ b/sysdeps/x86_64/multiarch/ifunc-memmove.h @@ -41,7 +41,8 @@ IFUNC_SELECTOR (void) { const struct cpu_features* cpu_features = __get_cpu_features (); - if (CPU_FEATURES_ARCH_P (cpu_features, Prefer_ERMS)) + if (CPU_FEATURES_ARCH_P (cpu_features, Prefer_ERMS) + || CPU_FEATURES_ARCH_P (cpu_features, Prefer_FSRM)) return OPTIMIZE (erms); if (CPU_FEATURES_ARCH_P (cpu_features, AVX512F_Usable) |