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authorWilco Dijkstra <wdijkstr@arm.com>2014-12-22 17:11:18 +0000
committerWilco Dijkstra <wdijkstr@arm.com>2014-12-22 17:14:55 +0000
commit8622d5568841458e801f8dd82846c5ba7e415f3e (patch)
tree004e03ed83e48e0274a831f66c4e30f3b4c2642f
parentf3806bdbc1d98c3392273837fcab86147212149d (diff)
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Optimize to avoid an unnecessary FPCR read.
-rw-r--r--ChangeLog5
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 2014-12-22  Wilco Dijkstra  <wdijkstr@arm.com>
 
+	* sysdeps/aarch64/fpu/feenablxcpt.c (feenableexcept):
+	Optimize to avoid an unnecessary FPCR read.
+
+2014-12-22  Wilco Dijkstra  <wdijkstr@arm.com>
+
 	* sysdeps/aarch64/fpu/fesetenv.c (fesetenv):
 	Optimize to reduce FPCR/FPSR accesses.