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| author | Tejas Belagod <Tejas.Belagod@arm.com> | 2022-07-05 11:35:24 +0100 |
|---|---|---|
| committer | Szabolcs Nagy <szabolcs.nagy@arm.com> | 2022-07-05 14:01:17 +0100 |
| commit | 05844d18f7893bf96965f163c428214fd5ebe10a (patch) | |
| tree | 53b241dc66872ef2effafb50bc5070b1397b616d | |
| parent | a9f9ee2381944cee8b4b50c5c8321e3529c77e49 (diff) | |
| download | glibc-05844d18f7893bf96965f163c428214fd5ebe10a.tar.gz glibc-05844d18f7893bf96965f163c428214fd5ebe10a.tar.xz glibc-05844d18f7893bf96965f163c428214fd5ebe10a.zip | |
AArch64: Reset HWCAP2_AFP bits in FPCR for default fenv
The AFP feature (Alternate floating-point behavior) was added in armv8.7 and introduced new FPCR bits. Currently, HWCAP2_AFP bits (bit 0, 1, 2) in FPCR are preserved when fenv is set to default environment. This is a deviation from standard behaviour. Clear these bits when setting the fenv to default. There is no libc API to modify the new FPCR bits. Restoring those bits matters if the user changed them directly.
| -rw-r--r-- | sysdeps/aarch64/fpu/fpu_control.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/sysdeps/aarch64/fpu/fpu_control.h b/sysdeps/aarch64/fpu/fpu_control.h index 764ed5cdbb..429f4910e7 100644 --- a/sysdeps/aarch64/fpu/fpu_control.h +++ b/sysdeps/aarch64/fpu/fpu_control.h @@ -46,7 +46,7 @@ contents. These two masks indicate which bits in each of FPCR and FPSR should not be changed. */ -#define _FPU_RESERVED 0xfe0fe0ff +#define _FPU_RESERVED 0xfe0fe0f8 #define _FPU_FPSR_RESERVED 0x0fffffe0 #define _FPU_DEFAULT 0x00000000 |