Fix sNaN handling in nearbyint on 32-bit sparc.

	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyint-vis3.S
	(__nearbyint_vis3): Don't check for sNaN before float register is
	loaded with the incoming argument.
	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyintf-vis3.S
	(__nearbyintf_vis3): Likewise.
	* sysdeps/sparc/sparc32/sparcv9/fpu/s_nearbyint.S (__nearbyint):
	Likewise.
	* sysdeps/sparc/sparc32/sparcv9/fpu/s_nearbyintf.S (__nearbyintf):
	Likewise.

(cherry picked from commit 3ef3f1b93fdf20143865cc16dd75f39a7f0fac2f)

5 files changed, 22 insertions, 10 deletions

diff --git a/ChangeLog b/ChangeLog
index 7ef0fe6006..b9b29b3ab1 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,15 @@
+2016-08-02  David S. Miller  <davem@davemloft.net>
+
+	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyint-vis3.S
+	(__nearbyint_vis3): Don't check for sNaN before float register is
+	loaded with the incoming argument.
+	* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyintf-vis3.S
+	(__nearbyintf_vis3): Likewise.
+	* sysdeps/sparc/sparc32/sparcv9/fpu/s_nearbyint.S (__nearbyint):
+	Likewise.
+	* sysdeps/sparc/sparc32/sparcv9/fpu/s_nearbyintf.S (__nearbyintf):
+	Likewise.
+
 2016-08-03  Aurelien Jarno  <aurelien@aurel32.net>
 
 	* sysdeps/powerpc/ifunc-sel.h (ifunc_sel): Replace beqlr instructions
diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyint-vis3.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyint-vis3.S
index d9ff0cc288..ff81b0da83 100644
--- a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyint-vis3.S
+++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyint-vis3.S
@@ -36,15 +36,15 @@
 #define SIGN_BIT	%f12			/* -0.0 */
 
 ENTRY (__nearbyint_vis3)
+	sllx	%o0, 32, %o0
+	or	%o0, %o1, %o0
+	movxtod	%o0, %f0
 	fcmpd	%fcc3, %f0, %f0			/* Check for sNaN */
 	st	%fsr, [%sp + 88]
 	sethi	%hi(TWO_FIFTYTWO), %o2
 	sethi	%hi(0xf8003e0), %o5
 	ld	[%sp + 88], %o4
-	sllx	%o0, 32, %o0
 	or	%o5, %lo(0xf8003e0), %o5
-	or	%o0, %o1, %o0
-	movxtod	%o0, %f0
 	andn	%o4, %o5, %o4
 	fzero	ZERO
 	st	%o4, [%sp + 80]
diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyintf-vis3.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyintf-vis3.S
index 5cd1eb02db..833a0dfc24 100644
--- a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyintf-vis3.S
+++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyintf-vis3.S
@@ -35,9 +35,9 @@
 #define SIGN_BIT	%f12			/* -0.0 */
 
 ENTRY (__nearbyintf_vis3)
+	movwtos	%o0, %f1
 	fcmps	%fcc3, %f1, %f1			/* Check for sNaN */
 	st	%fsr, [%sp + 88]
-	movwtos	%o0, %f1
 	sethi	%hi(TWO_TWENTYTHREE), %o2
 	sethi	%hi(0xf8003e0), %o5
 	ld	[%sp + 88], %o4
diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/s_nearbyint.S b/sysdeps/sparc/sparc32/sparcv9/fpu/s_nearbyint.S
index 84a10971a4..198440a5bc 100644
--- a/sysdeps/sparc/sparc32/sparcv9/fpu/s_nearbyint.S
+++ b/sysdeps/sparc/sparc32/sparcv9/fpu/s_nearbyint.S
@@ -36,21 +36,21 @@
 #define SIGN_BIT	%f12			/* -0.0 */
 
 ENTRY (__nearbyint)
+	sllx	%o0, 32, %o0
+	or	%o0, %o1, %o0
+	stx	%o0, [%sp + 72]
+	ldd	[%sp + 72], %f0
 	fcmpd	%fcc3, %f0, %f0			/* Check for sNaN */
 	st	%fsr, [%sp + 88]
 	sethi	%hi(TWO_FIFTYTWO), %o2
 	sethi	%hi(0xf8003e0), %o5
 	ld	[%sp + 88], %o4
-	sllx	%o0, 32, %o0
 	or	%o5, %lo(0xf8003e0), %o5
-	or	%o0, %o1, %o0
 	andn	%o4, %o5, %o4
 	fzero	ZERO
 	st	%o4, [%sp + 80]
-	stx	%o0, [%sp + 72]
 	sllx	%o2, 32, %o2
 	fnegd	ZERO, SIGN_BIT
-	ldd	[%sp + 72], %f0
 	ld	[%sp + 80], %fsr
 	stx	%o2, [%sp + 72]
 	fabsd	%f0, %f14
diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/s_nearbyintf.S b/sysdeps/sparc/sparc32/sparcv9/fpu/s_nearbyintf.S
index d5cf5ce815..9be41f6c22 100644
--- a/sysdeps/sparc/sparc32/sparcv9/fpu/s_nearbyintf.S
+++ b/sysdeps/sparc/sparc32/sparcv9/fpu/s_nearbyintf.S
@@ -35,9 +35,10 @@
 #define SIGN_BIT	%f12			/* -0.0 */
 
 ENTRY (__nearbyintf)
+	st	%o0, [%sp + 68]
+	ld	[%sp + 68], %f1
 	fcmps	%fcc3, %f1, %f1			/* Check for sNaN */
 	st	%fsr, [%sp + 88]
-	st	%o0, [%sp + 68]
 	sethi	%hi(TWO_TWENTYTHREE), %o2
 	sethi	%hi(0xf8003e0), %o5
 	ld	[%sp + 88], %o4
@@ -46,7 +47,6 @@ ENTRY (__nearbyintf)
 	fnegs	ZERO, SIGN_BIT
 	andn	%o4, %o5, %o4
 	st	%o4, [%sp + 80]
-	ld	[%sp + 68], %f1
 	ld	[%sp + 80], %fsr
 	st	%o2, [%sp + 68]
 	fabss	%f1, %f14