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| author | Gabriel F. T. Gomes <gftg@linux.vnet.ibm.com> | 2017-08-07 09:14:14 -0300 |
|---|---|---|
| committer | Gabriel F. T. Gomes <gftg@linux.vnet.ibm.com> | 2017-08-10 16:10:21 -0300 |
| commit | 4d98ace9de3183309cb394cd0110eda5ad2d2531 (patch) | |
| tree | f6467c5c3fa12f02f563e3d5d126ec1a6658e903 | |
| parent | 922369032c604b4dcfd535e1bcddd4687e7126a5 (diff) | |
| download | glibc-4d98ace9de3183309cb394cd0110eda5ad2d2531.tar.gz glibc-4d98ace9de3183309cb394cd0110eda5ad2d2531.tar.xz glibc-4d98ace9de3183309cb394cd0110eda5ad2d2531.zip | |
powerpc: Restrict xssqrtqp operands to Vector Registers (bug 21941)
POWER ISA 3.0 introduces the xssqrtqp instructions, which expects operands to be in Vector Registers (Altivec/VMX), even though this instruction belongs to the Vector-Scalar Instruction Set. In GCC's Extended Assembly for POWER, the 'wq' register constraint is provided for use with IEEE 754 128-bit floating-point values. However, this constraint does not limit the register allocation to Vector Registers (Altivec/VMX) and could assign a Vector-Scalar Register (VSX) to the operands of the instruction. This patch changes the register constraint used in sqrtf128 from 'wq' to 'v', in order to request a Vector Register (Altivec/VMX) for use with the xssqrtqp instruction. Tested for powerpc64le and --with-cpu=power9. [BZ #21941] * sysdeps/powerpc/fpu/math_private.h (__ieee754_sqrtf128): Since xssqrtqp requires operands to be in Vector Registers (Altivec/VMX), replace the register constraint 'wq' with 'v'. * sysdeps/powerpc/powerpc64le/power9/fpu/e_sqrtf128.c (__ieee754_sqrtf128): Likewise.
| -rw-r--r-- | ChangeLog | 9 | ||||
| -rw-r--r-- | sysdeps/powerpc/fpu/math_private.h | 2 | ||||
| -rw-r--r-- | sysdeps/powerpc/powerpc64le/power9/fpu/e_sqrtf128.c | 2 |
3 files changed, 11 insertions, 2 deletions
diff --git a/ChangeLog b/ChangeLog index e5e36a40e6..50db77f49a 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,12 @@ +2017-08-10 Gabriel F. T. Gomes <gftg@linux.vnet.ibm.com> + + [BZ #21941] + * sysdeps/powerpc/fpu/math_private.h (__ieee754_sqrtf128): Since + xssqrtqp requires operands to be in Vector Registers + (Altivec/VMX), replace the register constraint 'wq' with 'v'. + * sysdeps/powerpc/powerpc64le/power9/fpu/e_sqrtf128.c + (__ieee754_sqrtf128): Likewise. + 2017-08-10 Wilco Dijkstra <wdijkstr@arm.com> * sysdeps/aarch64/memcmp.S (memcmp): diff --git a/sysdeps/powerpc/fpu/math_private.h b/sysdeps/powerpc/fpu/math_private.h index d8fd4923ac..396fd0562e 100644 --- a/sysdeps/powerpc/fpu/math_private.h +++ b/sysdeps/powerpc/fpu/math_private.h @@ -30,7 +30,7 @@ extern __always_inline _Float128 __ieee754_sqrtf128 (_Float128 __x) { _Float128 __z; - asm ("xssqrtqp %0,%1" : "=wq" (__z) : "wq" (__x)); + asm ("xssqrtqp %0,%1" : "=v" (__z) : "v" (__x)); return __z; } #endif diff --git a/sysdeps/powerpc/powerpc64le/power9/fpu/e_sqrtf128.c b/sysdeps/powerpc/powerpc64le/power9/fpu/e_sqrtf128.c index 769d3f8922..59fd8269f5 100644 --- a/sysdeps/powerpc/powerpc64le/power9/fpu/e_sqrtf128.c +++ b/sysdeps/powerpc/powerpc64le/power9/fpu/e_sqrtf128.c @@ -30,7 +30,7 @@ __float128 __ieee754_sqrtf128 (__float128 a) { __float128 z; - asm ("xssqrtqp %0,%1" : "=wq" (z) : "wq" (a)); + asm ("xssqrtqp %0,%1" : "=v" (z) : "v" (a)); return z; } strong_alias (__ieee754_sqrtf128, __sqrtf128_finite) |