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| author | Adhemerval Zanella <adhemerval.zanella@linaro.org> | 2023-10-27 08:14:14 -0300 |
|---|---|---|
| committer | Adhemerval Zanella <adhemerval.zanella@linaro.org> | 2023-10-27 09:25:53 -0300 |
| commit | b0fe1533ff7283e765a2e590d210999ca045ca4c (patch) | |
| tree | df124095c3b1404230a2d4fb592242b6a7c95f60 | |
| parent | 4c023248ca791eefec5a7553057c0af3b9035f6c (diff) | |
| download | glibc-azanella/bz30944-memcpy-zen.tar.gz glibc-azanella/bz30944-memcpy-zen.tar.xz glibc-azanella/bz30944-memcpy-zen.zip | |
x86: Expand the comment on when REP STOSB is used on memset azanella/bz30944-memcpy-zen
| -rw-r--r-- | sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S b/sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S index 3d9ad49cb9..0821b32997 100644 --- a/sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S +++ b/sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S @@ -21,7 +21,9 @@ 2. If size is less than VEC, use integer register stores. 3. If size is from VEC_SIZE to 2 * VEC_SIZE, use 2 VEC stores. 4. If size is from 2 * VEC_SIZE to 4 * VEC_SIZE, use 4 VEC stores. - 5. If size is more to 4 * VEC_SIZE, align to 4 * VEC_SIZE with + 5. On machines ERMS feature, if size is greater or equal than + __x86_rep_stosb_threshold then REP STOSB will be used. + 6. If size is more to 4 * VEC_SIZE, align to 4 * VEC_SIZE with 4 VEC stores and store 4 * VEC at a time until done. */ #include <sysdep.h> |